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Coarse-fine gain-tracking loop and method of operating
(57) ABSTRACT A receiver gain tracking loop utilizing two Digital-to-Ana log Converters
(DACs) and methods for operating the gain tracking loop are provided. The gain tracking …
(DACs) and methods for operating the gain tracking loop are provided. The gain tracking …
Built-in jitter loading and state of polarization generation to characterize optical transceivers
(57) ABSTRACT A system includes an optical transmitter including a trans mitter Phase Lock
Loop (PLL) circuit; an optical receiver connected to the optical transmitter and including a …
Loop (PLL) circuit; an optical receiver connected to the optical transmitter and including a …
Estimating clock phase error based on channel conditions
Managing clock-data recovery for a modulated signal from a communication channel
comprises: receiving the modu lated signal and providing one or more analog signals …
comprises: receiving the modu lated signal and providing one or more analog signals …
Matching transmitters with receivers for making network-level assignments
the present disclosure generally relates to optical networking systems and methods. More
particularly, the present disclosure relates to matching transmitter components and receiver …
particularly, the present disclosure relates to matching transmitter components and receiver …
ADC self-calibration with on-chip circuit and method
A Vigneswaran, D Pollex - US Patent 11,558,061, 2023 - Google Patents
An ADC is a circuit that converts an analog signal to a digital signal. There is a need for
calibration of such circuits such as performed by using known reference vales and …
calibration of such circuits such as performed by using known reference vales and …
Jitter self-test using timestamps
RK Ranganathan, KV Jayakumar… - US Patent …, 2023 - Google Patents
(57) ABSTRACT A method for estimating jitter of a clock-signal-under-test includes
generating a phase-adjusted clock signal based on an input clock signal and a feedback …
generating a phase-adjusted clock signal based on an input clock signal and a feedback …
Method of controlling verification operations for error correction of non-volatile memory device, and non-volatile memory device
YK Yang, T Akaogi, P Chen - US Patent 11,119,854, 2021 - Google Patents
(57) ABSTRACT A method of controlling verification operations for error correction of a non-
volatile memory device includes the following. A tolerated error bit (TEB) number for error …
volatile memory device includes the following. A tolerated error bit (TEB) number for error …
Built-in jitter loading and state of polarization generation to characterize optical transceivers
2020-09-10 Assigned to CIENA CORPORATION reassignment CIENA CORPORATION
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …