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A strategy for using genetic algorithms to automate branch and fault-based testing
BF Jones, DE Eyres, HH Sthamer - the computer journal, 1998 - academic.oup.com
Genetic algorithms have been used successfully to generate software test data
automatically; all branches were covered with substantially fewer generated tests than …
automatically; all branches were covered with substantially fewer generated tests than …
A C4. 5 decision tree classifier based floorplanning algorithm for System-on-Chip design
Aggressive scaling technology in deep sub-micron System-on-Chip (SoC) design brings
various challenges to the Integrated Circuits (IC) designers. The significant challenges are …
various challenges to the Integrated Circuits (IC) designers. The significant challenges are …
A test pattern generation methodology for low power consumption
This paper proposes an ATPG technique that reduces power dissipation during the test of
sequential circuits. The proposed approach exploits some redundancy introduced during the …
sequential circuits. The proposed approach exploits some redundancy introduced during the …
Evolutionary algorithms for the physical design of VLSI circuits
Electronic design automation (EDA) is concerned with the design and production of VLSI
systems. One of the important steps in creating a VLSI circuit is physical design. The input to …
systems. One of the important steps in creating a VLSI circuit is physical design. The input to …
A genetic algorithm framework for test generation
Test generation using deterministic fault-oriented algorithms is highly complex and time
consuming. New approaches are needed to augment the existing techniques, both to …
consuming. New approaches are needed to augment the existing techniques, both to …
[ספר][B] Evolutionary algorithms for VLSI CAD
R Drechsler - 2013 - books.google.com
In VLSI CAD, difficult optimization problems have to be solved on a constant basis. Various
optimization techniques have been proposed in the past. While some of these methods have …
optimization techniques have been proposed in the past. While some of these methods have …
A genetic algorithm-based heuristic method for test set generation in reversible circuits
Low power circuit design has been one of the major growing concerns in integrated circuit
technology. Reversible circuit (RC) design is a promising future domain in computing which …
technology. Reversible circuit (RC) design is a promising future domain in computing which …
Genetic algorithm based software testing
In this work we axe studying possibilities to test software using genetic algorithm search. The
idea is to produce test cases in order to find problematic situations like processing time …
idea is to produce test cases in order to find problematic situations like processing time …
Testability analysis and ATPG on behavioral RT-level VHDL
This paper proposes an environment to address testability analysis and test pattern
generation on VHDL descriptions at the RT-level. The proposed approach, based on a …
generation on VHDL descriptions at the RT-level. The proposed approach, based on a …
An RT-level fault model with high gate level correlation
With the advent of new RT-level design and test flows, new tools are needed to migrate at
the RT-level the activities of fault simulation testability analysis, and test pattern generation …
the RT-level the activities of fault simulation testability analysis, and test pattern generation …