Llm for soc security: A paradigm shift

D Saha, S Tarek, K Yahyaei, SK Saha, J Zhou… - IEEE …, 2024 - ieeexplore.ieee.org
As the ubiquity and complexity of system-on-chip (SoC) designs increase across electronic
devices, incorporating security into an SoC design flow poses significant challenges …

Ryoan: A distributed sandbox for untrusted computation on secret data

T Hunt, Z Zhu, Y Xu, S Peter, E Witchel - ACM Transactions on Computer …, 2018 - dl.acm.org
Users of modern data-processing services such as tax preparation or genomic screening
are forced to trust them with data that the users wish to keep secret. Ryoan1 protects secret …

SoK: Computer-aided cryptography

M Barbosa, G Barthe, K Bhargavan… - … IEEE symposium on …, 2021 - ieeexplore.ieee.org
Computer-aided cryptography is an active area of research that develops and applies
formal, machine-checkable approaches to the design, analysis, and implementation of …

A hardware design language for timing-sensitive information-flow security

D Zhang, Y Wang, GE Suh, AC Myers - Acm Sigplan Notices, 2015 - dl.acm.org
Information security can be compromised by leakage via low-level hardware features. One
recently prominent example is cache probing attacks, which rely on timing channels created …

The unpatchable silicon: a full break of the bitstream encryption of xilinx 7-series {FPGAs}

M Ender, A Moradi, C Paar - 29th USENIX Security Symposium (USENIX …, 2020 - usenix.org
The security of FPGAs is a crucial topic, as any vulnerability within the hardware can have
severe consequences, if they are used in a secure design. Since FPGA designs are …

{TheHuzz}: Instruction fuzzing of processors using {Golden-Reference} models for finding {Software-Exploitable} vulnerabilities

R Kande, A Crump, G Persyn, P Jauernig… - 31st USENIX Security …, 2022 - usenix.org
The increasing complexity of modern processors poses many challenges to existing
hardware verification tools and methodologies for detecting security-critical bugs. Recent …

{HardFails}: insights into {software-exploitable} hardware bugs

G Dessouky, D Gens, P Haney, G Persyn… - 28th USENIX Security …, 2019 - usenix.org
Modern computer systems are becoming faster, more efficient, and increasingly
interconnected with each generation. Thus, these platforms grow more complex, with new …

Register transfer level information flow tracking for provably secure hardware design

A Ardeshiricham, W Hu, J Marxen… - Design, Automation & …, 2017 - ieeexplore.ieee.org
Information Flow Tracking (IFT) provides a formal methodology for modeling and reasoning
about security properties related to integrity, confidentiality, and logical side channel …

A formal foundation for secure remote execution of enclaves

P Subramanyan, R Sinha, I Lebedev… - Proceedings of the …, 2017 - dl.acm.org
Recent proposals for trusted hardware platforms, such as Intel SGX and the MIT Sanctum
processor, offer compelling security features but lack formal guarantees. We introduce a …

{CacheD}: Identifying {Cache-Based} timing channels in production software

S Wang, P Wang, X Liu, D Zhang, D Wu - 26th USENIX security …, 2017 - usenix.org
Side-channel attacks recover secret information by analyzing the physical implementation of
cryptosystems based on non-functional computational characteristics, eg time, power, and …