(57) ABSTRACT A suite of novel structures and methods is provided to reduce power
consumption in a wide array of electronic devices and systems. Some of these structures …

6,808 004 B2 10/2004 Kamm et a1, 7,398,497 B2 7/2008 Sato et 31. 63083994 B1 10/2004
Wang 7,402,207 B1 7/2008 Besser et a1. 6,813,750 B2 11/2004 Usami et 31 ' 7,402,872 B2 …

Some structures and methods to reduce power consumption in devices can be implemented
largely by reusing existing bulk CMOS process flows and manufacturing technology …

Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced
OV, compared to conven tional bulk CMOS and can allow the threshold voltage V of FETs …

An advanced transistor with punch through suppression includes a gate with length Lg, a
well doped to have a? rst concentration of a dopant, and a screening region positioned …

5,144,378 5,156,989 5,156,990 5,166,765 5,208.473 5,294,821 5,298.763 5,369,288 5,373,
186 5,384,476 5,426.328 5,444,008 5,552,332 5,559,368 5,608,253 5,622,880 5,624,863 …

(65) Prior Publication Data(Continued) US 2014/O119099 A1 May 1, 2014 Primary
Examiner—Andrew Q Tran (74) Attorney, Agent, or Firm—Baker Botts LLP Related US …

Stress is introduced into the channel of an SOI FinFET device by transfer directly from a
metal gate. In SOI devices in particular, stress transfer efficiency from the metal gate to the …

Techniques for employing different channel materials within the same CMOS circuit are
provided. In one aspect, a method of fabricating a CMOS circuit includes the following steps …

(57) ABSTRACT A method for forming a semiconductor device includes forming a first
channel region and a second channel region on a substrate, depositing a dielectric material …