[HTML][HTML] A survey study on virtual machine migration and server consolidation techniques in DVFS-enabled cloud datacenter: taxonomy and challenges

MH Shirvani, AM Rahmani, A Sahafi - Journal of King Saud University …, 2020 - Elsevier
Cloud Computing is a promising paradigm in comparison with traditional information
technology approaches, in which organizations and enterprises adopt elastic cloud services …

A survey of architectural techniques for improving cache power efficiency

S Mittal - Sustainable Computing: Informatics and Systems, 2014 - Elsevier
Modern processors are using increasingly larger sized on-chip caches. Also, with each
CMOS technology generation, there has been a significant increase in their leakage energy …

RAPL: Memory power estimation and cap**

H David, E Gorbatov, UR Hanebutte… - Proceedings of the 16th …, 2010 - dl.acm.org
The drive for higher performance and energy efficiency in data-centers has influenced
trends toward increased power and cooling requirements in the facilities. Since enterprise …

Pack & cap: adaptive dvfs and thread packing under power caps

R Cochran, C Hankendi, AK Coskun… - Proceedings of the 44th …, 2011 - dl.acm.org
The ability to cap peak power consumption is a desirable feature in modern data centers for
energy budgeting, cost management, and efficient power delivery. Dynamic voltage and …

Temperature-constrained power control for chip multiprocessors with online model estimation

Y Wang, K Ma, X Wang - ACM SIGARCH computer architecture news, 2009 - dl.acm.org
As chip multiprocessors (CMP) become the main trend in processor development, various
power and thermal management strategies have recently been proposed to optimize system …

RapidMRC: approximating L2 miss rate curves on commodity systems for online optimizations

DK Tam, R Azimi, LB Soares, M Stumm - ACM Sigplan Notices, 2009 - dl.acm.org
Miss rate curves (MRCs) are useful in a number of contexts. In our research, online L2 cache
MRCs enable us to dynamically identify optimal cache sizes when cache-partitioning a …

Scalable thread scheduling and global power management for heterogeneous many-core architectures

JA Winter, DH Albonesi, CA Shoemaker - Proceedings of the 19th …, 2010 - dl.acm.org
Future many-core microprocessors are likely to be heterogeneous, by design or due to
variability and defects. The latter type of heterogeneity is especially challenging due to its …

Scalable power control for many-core architectures running multi-threaded applications

K Ma, X Li, M Chen, X Wang - Proceedings of the 38th annual …, 2011 - dl.acm.org
Optimizing the performance of a multi-core microprocessor within a power budget has
recently received a lot of attention. However, most existing solutions are centralized and …

How much power oversubscription is safe and allowed in data centers

X Fu, X Wang, C Lefurgy - Proceedings of the 8th ACM international …, 2011 - dl.acm.org
Data centers attempt to maximize return on investment by achieving high levels of utilization.
This means deploying the maximum number of servers possible within existing power …

Using multiple input, multiple output formal control to maximize resource efficiency in architectures

RP Pothukuchi, A Ansari, P Voulgaris… - ACM SIGARCH …, 2016 - dl.acm.org
As processors seek more resource efficiency, they increasingly need to target multiple goals
at the same time, such as a level of performance, power consumption, and average …