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Performing power management in a multicore processor
In an embodiment, a processor includes: a plurality of first cores to independently execute
instructions, each of the plurality of first cores including a plurality of counters to store …
instructions, each of the plurality of first cores including a plurality of counters to store …
Multi-CPU system and multi-CPU system scaling method
T Nakagawa - US Patent 9,996,400, 2018 - Google Patents
In an asymmetric multi-CPU system on which a plurality of type of CPUs with different data
processing performance and power consumption are mounted in groups for each type, a …
processing performance and power consumption are mounted in groups for each type, a …
Energy efficient multi-cluster system and its operations
JM Chen, HL Chou, YT Chang, SY Chiu… - US Patent …, 2018 - Google Patents
(57) ABSTRACT A multi-cluster system having processor cores of different energy efficiency
characteristics is configured to operate with high efficiency such that performance and power …
characteristics is configured to operate with high efficiency such that performance and power …
Switching tasks between heterogeneous cores
O Zaarur, P Sakarda - US Patent 9,069,553, 2015 - Google Patents
The present disclosure describes techniques for Switching tasks between heterogeneous
cores. In some aspects it is determined that a task being executed by a first core of a …
cores. In some aspects it is determined that a task being executed by a first core of a …
Systems, methods and devices for work placement on processor cores
G Therien, G Sotomayor, A Biswas, MD Powell… - US Patent …, 2018 - Google Patents
Work can be migrated between processor cores. For example, a thread causing a heavy
load on a first core can be detected. A power control unit can determine to migrate the thread …
load on a first core can be detected. A power control unit can determine to migrate the thread …
Method of scheduling threads for execution on multiple processors within an information handling system
TA Shows - US Patent 9,342,374, 2016 - Google Patents
(57) ABSTRACT A method for improving thread execution speed within a multi-processor
system includes a first processor and a sec ond processor. The first processor generates …
system includes a first processor and a sec ond processor. The first processor generates …
Heterogeneous thread scheduling
NK Singh, TA Brown, JS Samli, JS Wohlgemuth… - US Patent …, 2016 - Google Patents
(57) ABSTRACT US 2016/0092274 A1 Mar. 31, 2016 Heterogeneous thread scheduling
techniques are described in (51) Int. Cl. which a processing workload is distributed to …
techniques are described in (51) Int. Cl. which a processing workload is distributed to …
Performing power management in a multicore processor
(74) Attorney, Agent, or Firm—Trop, Pruner & Hu, PC (57) ABSTRACT In an embodiment, a
processor a plurality of cores to independently execute instructions, the cores including a …
processor a plurality of cores to independently execute instructions, the cores including a …
Processing system including a plurality of cores and method of operating the same
KS Yu, KI Sun, CH Youn - US Patent 10,255,118, 2019 - Google Patents
(57) ABSTRACT A system and method of allocating resources among cores in a multi-core
system is disclosed. The system and method determine cores that are able to process tasks …
system is disclosed. The system and method determine cores that are able to process tasks …
Self-referenced sense amplifier for spin torque MRAM
Circuitry and a method provide a plurality of timed control and bias Voltages to sense
amplifiers and write drivers of a spin-torque magnetoresistive random access memory array …
amplifiers and write drivers of a spin-torque magnetoresistive random access memory array …