A system for executing instructions using a plurality of register file segments for a processor.
The system includes a global front end scheduler for receiving an incoming instruction …

(57) ABSTRACT A method for dependency broadcasting through a source organized source
view data structure. The method includes receiving an incoming instruction sequence using …

BACKGROUND Two types of processor architectures are widely recog nized in the field of
computer science:“scalar and “vector. A Scalar processor is designed to execute instructions …

A method for dependency broadcasting through a block organized source view data
structure. The method includes receiving an incoming instruction sequence using a global …

A method for predicting a way of a set associative shadow cache is disclosed. As a part of a
method, a request to fetch a first far taken branch instruction of a first cache line from an …

A method for executing dual dispatch of blocks and half blocks. The method includes
receiving an incoming instruction sequence using a global front end; grou** the …

Instructions and logic provide SIMD address conflict detection functionality. Some
embodiments include processors with a register with a variable plurality of data fields, each …

A method for implementing a reduced size register view data structure in a microprocessor.
The method includes receiving an incoming instruction sequence using a global front end; …

(57) ABSTRACT A method for executing multithreaded instructions grouped into blocks. The
method includes receiving an incoming instruction sequence using a global front end; …

A method for emulating a guest centralized flag architecture by using a native distributed flag
architecture. The method includes receiving an incoming instruction sequence using a …