CHERI extends a conventional RISC Instruction-Set Architecture, compiler, and operating
system to support fine-grained, capability-based memory protection to mitigate memory …

Industry is building larger, more complex, manycore processors on the back of strong
institutional knowledge, but academic projects face difficulties in replicating that scale. To …

This technical report describes CHERI ISAv7, the seventh version of the Capability
Hardware Enhanced RISC Instructions (CHERI) Instruction-Set Architecture (ISA) being …

Embedded systems are deployed ubiquitously among various sectors including automotive,
medical, robotics and avionics. As these devices become increasingly connected, the attack …

Architectures targeted at embedded systems often have limited floating point computation
capabilities, and in many cases do not provide any hardware support. In this work, we …

This technical report describes CHERI ISAv4, the fourth version of the Capability Hardware
Enhanced RISC Instructions (CHERI) Instruction-Set Architecture (ISA). CHERI is being …

Cloud computing has hugely impacted over the last few decades the Information
Technology (IT) industry by offering virtually unlimited storage and processing capabilities at …

Sail is a language for expressing the instruction-set architecture (ISA) semantics of
processors. Vendor architecture specification documents typically describe the sequential …

Compartmentalisation is a technique to reduce the impact of security bugs by enforcing the
'principle of least privilege'within applications. Splitting programs into separate components …

Capability Hardware Enhanced RISC Instructions: CHERI Programmer's Guide Page 1
Technical Report Number 877 Computer Laboratory UCAM-CL-TR-877 ISSN 1476-2986 …