Making convolutions resilient via algorithm-based error detection techniques

SKS Hari, MB Sullivan, T Tsai… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
Convolutional Neural Networks (CNNs) are being increasingly used in safety-critical and
high-performance computing systems. As such systems require high levels of resilience to …

[HTML][HTML] Open-source IP cores for space: A processor-level perspective on soft errors in the RISC-V era

S Di Mascio, A Menicucci, E Gill, G Furano… - Computer Science …, 2021 - Elsevier
This paper discusses principles and techniques to evaluate processors for dependable
computing in space applications. The focus is on soft errors, which dominate the failure rate …

Optimizing software-directed instruction replication for gpu error detection

A Mahmoud, SKS Hari, MB Sullivan… - … Conference for High …, 2018 - ieeexplore.ieee.org
Application execution on safety-critical and high-performance computer systems must be
resilient to transient errors. As GPUs become more pervasive in such systems, they must …

Hardnn: Feature map vulnerability evaluation in cnns

A Mahmoud, SKS Hari, CW Fletcher, SV Adve… - arxiv preprint arxiv …, 2020 - arxiv.org
As Convolutional Neural Networks (CNNs) are increasingly being employed in safety-critical
applications, it is important that they behave reliably in the face of hardware errors. Transient …

Run-time reconfigurable MPSoC-based on-board processor for vision-based space navigation

A Pérez, A Rodríguez, A Otero, DG Arjona… - IEEE …, 2020 - ieeexplore.ieee.org
This paper describes a reconfigurable architecture for an on-board processor to be used in
space exploration critical systems. It relies on, a dynamically reconfigurable multi …

The Arm triple core lock-step (TCLS) processor

X Iturbe, B Venu, E Ozer, JL Poupat… - ACM Transactions on …, 2019 - dl.acm.org
The Arm Triple Core Lock-Step (TCLS) architecture is the natural evolution of Arm Cortex-R
Dual Core Lock-Step (DCLS) processors to increase dependability, predictability, and …

Soft error vulnerability assessment of the real-time safety-related ARM Cortex-R5 CPU

X Iturbe, B Venu, E Ozer - … on Defect and Fault Tolerance in …, 2016 - ieeexplore.ieee.org
This paper presents the results collected in a series of fault injection experiments conducted
on a modern commercial embedded ARM Cortex-R5 processor, which is extensively used in …

Variable delayed dual-core lockstep (vdcls) processor for safety and security applications

K Marcinek, WA Pleskacz - Electronics, 2023 - mdpi.com
Dual-Core Lockstep (DCLS) is one of the most commonly used techniques in applications
requiring functional safety. As the semiconductor process nodes keep shrinking, the DCLS …

Scalable parallel flash firmware for many-core architectures

J Zhang, M Kwon, M Swift, M Jung - 18th USENIX Conference on File …, 2020 - usenix.org
NVMe is designed to unshackle flash from a traditional storage bus by allowing hosts to
employ many threads to achieve higher bandwidth. While NVMe enables users to fully …

Particle filtering with factorized likelihoods for tracking facial features

I Patras, M Pantic - … Conference on Automatic Face and Gesture …, 2004 - ieeexplore.ieee.org
In the recent years particle filtering has been the dominant paradigm for tracking facial and
body features, recognizing temporal events and reasoning in uncertainty. A major problem …