An analog fractional-sampling phase-locked loop (PLL) is presented. It achieves 75-fs rms
jitter, integrated from 10 kHz to 10 MHz, and a− 249.7-dB figure of merit (FoM) at the …

5G is the latest global wireless standard, known as the fifth generation of cellular mobile
communication technology. Compared to 4G LTE, 5G increases peak data rates and …

This article presents a fractional-N frequency synthesizer architecture that is able to
overcome the limitations of conventional bang-bang phase-locked loops. A digital …

In this paper, we present an all-digital ring oscillator (RO)-based Bluetooth low-energy (BLE)
transmitter (TX) for ultra-low-power radios in short range Internet-of-Things (IoT) …

A conventional figure-of-merit (FOM) for a phase-locked loop (PLL) has served as the most
powerful indicator to compare and to normalize performance of different PLL designs …

This article proposes a fractional-N digital phase-locked loop (DPLL) that achieves a 265-
μW ultra-lowpower operation. The proposed switching feedback can seamlessly change the …

This paper presents a sub-mW fractional-N all-digital phase-locked loop (ADPLL) with
scalable power consumption, which achieves an figure of merit (FOM) of-246 dB. The …

Ultra-low-jitter and high-spectral-purity frequency synthesizers are key building blocks for
high-performance wireless transceivers and FMCW radars. A bang-bang PLL(BBPLL) is an …

This article proposes a power-efficient highly linear capacitor-array-based digital-to-time
converter (DTC) using a charge redistribution constant-slope approach. A fringe-capacitor …

This paper presents a power-efficient constant-slope digital-to-time converter (DTC) with
embedded nonlinearity cancellation. By utilizing the capacitor based digital-to-analog …