Advanced fabrication processes for superconducting very large-scale integrated circuits
SK Tolpygo, V Bolkhovsky, TJ Weir… - IEEE Transactions …, 2016 - ieeexplore.ieee.org
We review the salient features of two advanced nodes of an 8-Nb-layer fully planarized
process developed recently at MIT Lincoln Laboratory for fabricating single flux quantum …
process developed recently at MIT Lincoln Laboratory for fabricating single flux quantum …
Fabrication Process and Properties of Fully-Planarized Deep-Submicron Nb/Al– Josephson Junctions for VLSI Circuits
SK Tolpygo, V Bolkhovsky, TJ Weir… - IEEE transactions on …, 2014 - ieeexplore.ieee.org
A fabrication process for Nb/Al-AlO x/Nb Josephson junctions (JJs) with sizes down to 200
nm has been developed on a 200-mm-wafer tool set typical for CMOS foundry. This process …
nm has been developed on a 200-mm-wafer tool set typical for CMOS foundry. This process …
Advanced fabrication processes for superconductor electronics: Current status and new developments
In superconductor electronics fabrication processes developed at MIT Lincoln Laboratory,
Josephson junctions (JJs) are placed near the top of the stack composed of nine or ten …
Josephson junctions (JJs) are placed near the top of the stack composed of nine or ten …
Inductance of superconductor integrated circuit features with sizes down to 120 nm
Data are presented on the inductance of various features used in superconductor digital
integrated circuits: microstrip and stripline inductors with linewidths down to 120 nm and …
integrated circuits: microstrip and stripline inductors with linewidths down to 120 nm and …
Improved coherence in optically defined niobium trilayer-junction qubits
Niobium offers the benefit of increased operating temperatures and frequencies for
Josephson junctions, which are the core component of superconducting devices. However …
Josephson junctions, which are the core component of superconducting devices. However …
High density fabrication process for single flux quantum circuits
D Yohannes, M Renzullo, J Vivalda, AC Jacobs… - Applied Physics …, 2023 - pubs.aip.org
We implemented, optimized, and fully tested a superconducting Josephson junction
fabrication process over multiple runs tailored for integrated digital circuits that are used for …
fabrication process over multiple runs tailored for integrated digital circuits that are used for …
Deep sub-micron stud-via technology of superconductor VLSI circuits
SK Tolpygo, V Bolkhovsky, T Weir… - Superconductor …, 2014 - iopscience.iop.org
A fabrication process has been developed for fully planarized Nb-based superconducting
interlayer connections (vias) with minimum size down to 250 nm for superconductor very …
interlayer connections (vias) with minimum size down to 250 nm for superconductor very …
System and method for providing multi-conductive layer metallic interconnects for superconducting integrated circuits
Superconducting integrated circuits require several wiring layers to distribute bias and
signals across the circuit, which must cross each other both with and without contacts. All …
signals across the circuit, which must cross each other both with and without contacts. All …
Planarized, extendible, multilayer fabrication process for superconducting electronics
DT Yohannes, RT Hunt, JA Vivalda… - IEEE Transactions …, 2014 - ieeexplore.ieee.org
We report on technique and results for superconductor electronics fabrication process,
featuring customizable number of planarized superconducting layers. The novel technique …
featuring customizable number of planarized superconducting layers. The novel technique …
Disentangling superconductor and dielectric microwave losses in submicrometer / interconnects using a multimode microstrip resonator
An understanding of the origins of power loss in superconducting interconnects is essential
for the energy efficiency and scalability of superconducting digital logic. At microwave …
for the energy efficiency and scalability of superconducting digital logic. At microwave …