Optical RAM and integrated optical memories: a survey
The remarkable achievements in the area of integrated optical memories and optical
random access memories (RAMs) together with the rapid adoption of optical interconnects in …
random access memories (RAMs) together with the rapid adoption of optical interconnects in …
SRAM cell design challenges in modern deep sub-micron technologies: An overview
W Gul, M Shams, D Al-Khalili - Micromachines, 2022 - mdpi.com
Microprocessors use static random-access memory (SRAM) cells in the cache memory
design. As a part of the central computing component, their performance is critical. Modern …
design. As a part of the central computing component, their performance is critical. Modern …
A comprehensive analysis of different 7T SRAM topologies to design a 1R1 W bit interleaving enabled and half select free cell for 32 nm technology node
In this paper, a single-ended, dual port, 1R1 W seven transistor-based static random access
memory bit cell is presented. The cell is designed based on a detailed review of various pre …
memory bit cell is presented. The cell is designed based on a detailed review of various pre …
10T SRAM Using Half- Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage
N Maroof, BS Kong - IEEE transactions on very large scale …, 2016 - ieeexplore.ieee.org
We present, in this paper, a new 10T static random access memory cell having single ended
decoupled read-bitline (RBL) with a 4T read port for low power operation and leakage …
decoupled read-bitline (RBL) with a 4T read port for low power operation and leakage …
Process variation aware analysis of SRAM SEU cross sections using data retention voltage
D Kobayashi, N Hayashi, K Hirose… - … on Nuclear Science, 2018 - ieeexplore.ieee.org
Static random access memory (SRAM) is one the most sensitive devices to radiation. It may
often exhibit undesired reversals of memory bits, called single-event upsets or soft errors …
often exhibit undesired reversals of memory bits, called single-event upsets or soft errors …
An embedded level-shifting dual-rail sram for high-speed and low-power cache
An embedded level-shifting (ELS) dual-rail SRAM is proposed to enhance the availability of
dual-rail SRAMs. Although dual-rail SRAM is a powerful solution for satisfying the increasing …
dual-rail SRAMs. Although dual-rail SRAM is a powerful solution for satisfying the increasing …
8T1R: A novel low-power high-speed RRAM-based non-volatile SRAM design
With continuous and aggressive technology scaling, suppressing the stand-by power is
among the top priorities for SRAM design. Switching off the less-frequently accessed blocks …
among the top priorities for SRAM design. Switching off the less-frequently accessed blocks …
Effect of the radial ionization profile of proton on SEU sensitivity of nanoscale SRAMs
This paper investigates the impact of the radial ionization profile of proton on SEU sensitivity
for nanoscale devices. Intrinsic radial track structures of energy deposition of protons (from …
for nanoscale devices. Intrinsic radial track structures of energy deposition of protons (from …
Neutron-induced multiple-cell upsets in 20-nm bulk SRAM: Angular sensitivity and impact of multiwell potential perturbation
T Kato, T Yamazaki, N Saito… - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
Neutron-induced multiple-cell upsets (MCUs) are studied in a 20-nm bulk SRAM by
irradiation experiments using atmospheric-like neutrons at several angles of incidence. The …
irradiation experiments using atmospheric-like neutrons at several angles of incidence. The …
Generalized water-filling for source-aware energy-efficient SRAMs
Conventional low-power static random access memories (SRAMs) reduce read energy by
decreasing the bit-line voltage swings uniformly across the bit-line columns. This is because …
decreasing the bit-line voltage swings uniformly across the bit-line columns. This is because …