A 1.5-3.3 GHz, 7 mW, all-digital delay-locked loop (ADDLL) designed in a UMC 130-nm
CMOS technology is presented in this paper. The proposed ADDLL uses the modified …

This brief presents a phase rotator (PR)-based delay-locked loop (DLL) for a dynamic
random-access memory interface in 28-nm CMOS technology. A direct input–output …

Conventional structure of delay locked loops (DLLs) is modified to achieve better jitter and
smaller lock time. In the proposed structure, analog charge pump is eliminated, to remove …

This article describes a dual-controller dual-delay line delay lock loop (DC-DL DLL). The
proposed DLL adopted a dual delay line structure, each delay line was composed of a …

A new high-speed, low-power, and fast-lock all-digital delay-locked loop (DLL) for high-
speed next-generation memory interface is presented. The proposed all-digital DLL utilizes …

This paper presents a fast lock-in time clock frequency multiplier without using traditional
clock generation circuits such as PLLs and DLLs. We propose a novel technique based on …

This paper presents a mixed-mode delay-locked loop (MM-DLL) with binary search (BS)
locking, designed to cover a broad frequency range from 533 MHz to 4.2 GHz. The BS …

In this paper, a time-variant analysis is made on Single-Event Transients (SETs) in
integrated CMOS ring oscillators. The Impulse Sensitive Function (ISF) of the oscillator is …

An all-digital delay-locked loop (DLL) for a mobile memory interface, which runs at 0.11-2.5
GHz with a phase-shift capability of $180^{\circ} $, has two internal DLLs: a global DLL …

This paper presents a new fast-lock all-digital delay-locked loop (DLL) for next-generation
memory devices such as DDR5 SDRAMs. The proposed DLL utilizes a new two-step time-to …