GenMC: A Model Checker for Weak Memory Models
GenMC is an LLVM-based state-of-the-art stateless model checker for concurrent C/C++
programs. Its modular infrastructure allows it to support complex memory models, such as …
programs. Its modular infrastructure allows it to support complex memory models, such as …
Choice trees: Representing nondeterministic, recursive, and impure programs in coq
This paper introduces ctrees, a monad for modeling nondeterministic, recursive, and impure
programs in Coq. Inspired by **a et al.'s itrees, this novel data structure embeds …
programs in Coq. Inspired by **a et al.'s itrees, this novel data structure embeds …
Compass: strong and compositional library specifications in relaxed memory separation logic
Several functional correctness criteria have been proposed for relaxed-memory consistency
libraries, but most lack support for modular client reasoning. Mével and Jourdan recently …
libraries, but most lack support for modular client reasoning. Mével and Jourdan recently …
What's Decidable About Causally Consistent Shared Memory?
While causal consistency is one of the most fundamental consistency models weaker than
sequential consistency, the decidability of safety verification for (finite-state) concurrent …
sequential consistency, the decidability of safety verification for (finite-state) concurrent …
A two-phase infinite/finite low-level memory model: Reconciling integer–pointer casts, finite space, and undef at the llvm ir level of abstraction
This paper provides a novel approach to reconciling complex low-level memory model
features, such as pointer--integer casts, with desired refinements that are needed to justify …
features, such as pointer--integer casts, with desired refinements that are needed to justify …
The leaky semicolon: compositional semantic dependencies for relaxed-memory concurrency
Program logics and semantics tell a pleasant story about sequential composition: when
executing (S1; S2), we first execute S1 then S2. To improve performance, however …
executing (S1; S2), we first execute S1 then S2. To improve performance, however …
Lasagne: a static binary translator for weak memory model architectures
The emergence of new architectures create a recurring challenge to ensure that existing
programs still work on them. Manually porting legacy code is often impractical. Static binary …
programs still work on them. Manually porting legacy code is often impractical. Static binary …
Unifying operational weak memory verification: an axiomatic approach
In this article, we propose an approach to program verification using an abstract
characterisation of weak memory models. Our approach is based on a hierarchical axiom …
characterisation of weak memory models. Our approach is based on a hierarchical axiom …
Extending Intel-x86 consistency and persistency: formalising the semantics of Intel-x86 memory types and non-temporal stores
Existing semantic formalisations of the Intel-x86 architecture cover only a small fragment of
its available features that are relevant for the consistency semantics of multi-threaded …
its available features that are relevant for the consistency semantics of multi-threaded …
Semantics of Remote Direct Memory Access: Operational and Declarative Models of RDMA on TSO Architectures
Remote direct memory access (RDMA) is a modern technology enabling networked
machines to exchange information without involving the operating system of either side, and …
machines to exchange information without involving the operating system of either side, and …