Reconfigurable FPGA architectures: A survey and applications

P Babu, E Parthasarathy - Journal of The Institution of Engineers (India) …, 2021 - Springer
Reconfigurable computing is a potential paradigm which has been effectively performing
mostly in the developments of devices likely Field Programmable Gate Arrays (FPGAs). This …

FPGA implementation of high performance digital down converter for software defined radio

D Datta, P Mitra, HS Dutta - Microsystem Technologies, 2022 - Springer
Digital down converter (DDC) is one of the crucial components in digital radio receiver. The
working function of DDC is to convert the frequency translation from Intermediate Frequency …

Power-and area-optimized high-level synthesis implementation of a digital down converter for software-defined radio applications

P Sikka, AR Asati, C Shekhar - Circuits, Systems, and Signal Processing, 2021 - Springer
In digital signal processing, digital down converters (DDCs) convert digitized, band-limited
signals to lower frequency signals at a smaller sampling rate to simplify subsequent filtering …

Implementation of polyphase digital down converter for wireless applications

D Datta, HS Dutta - Microprocessors and Microsystems, 2023 - Elsevier
This paper briefs the hardware-efficient polyphase digital down converter (DDC), which
reduces the input sampling frequency to 3.64 GHz and produces a complex output to meet …

High efficient polyphase digital down converter on FPGA

D Datta, HS Dutta - Circuits, Systems, and Signal Processing, 2021 - Springer
This paper presents an implementation of a reconfigurable digital down converter (DDC)
that can translate high sample rate to lower sample rate signal on field-programmable gate …

Design and Implementation of Digital Down Converter for WiFi Network

D Datta, HS Dutta - IEEE Embedded Systems Letters, 2023 - ieeexplore.ieee.org
This letter introduces a field-programmable gate array (FPGA)-based digital down converter
(DDC) processing a sampling frequency of about 3.64 GHz to a down-converted frequency …

Dual-Frequency, Dual-Mode Reconfigurable Digital Atmospheric Radar Receiver Design

Z Zhang, Q Xu, X Hu, B Cai, Y Wu, J Yang, M Zhao - Electronics, 2024 - mdpi.com
A new dual-frequency, dual-mode reconfigurable digital receiver based on Field-
Programmable Gate Array (FPGA) dynamic reconfiguration is proposed, which is based on a …

High Efficient Half-Band Decimation Filter on FPGA

D Datta, HS Dutta - Transactions of the Indian National Academy of …, 2023 - Springer
Linear-phase half-band (HB) finite impulse response (FIR) filters are indispensable in
multirate signal processing applications. This paper briefs the design and implementation of …

[PDF][PDF] Enhanced signal processing through FPGA-based digital downconversion via the CORDIC algorithm

M Yin, Y Jiang - J. Ind Intell, 2024 - library.acadlore.com
To address the rate matching issue between high-bandwidth and high-sampling-rate analog-
to-digital converters (ADCs) and low-bandwidth and low-sampling-rate baseband …

Implementation of fractional sample rate digital down converter for radio receiver applications

D Datta, P Mitra, HS Dutta - 2021 Devices for Integrated Circuit …, 2021 - ieeexplore.ieee.org
This paper briefs a novel approach of field-programmable gate array (FPGA) based
fractional sample rate digital down converter (FSRDDC) which reduces the sample rate from …