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FPGA having logic cells configured by SRAM memory cells and interconnect configured by antifuses
FE Goetting - US Patent 5,744,979, 1998 - Google Patents
An FPGA combines antifuse and static memory cell pro graming technologies. Static
memory cells determine the functions of the FPGA logic cells. Antifuses establish rout ing …
memory cells determine the functions of the FPGA logic cells. Antifuses establish rout ing …
Programmable structured arrays
RU Madurawe - US Patent 7,030,651, 2006 - Google Patents
BACKGROUND The present invention relates to programmable structured arrays for
semiconductor integrated circuits. Traditionally, application specific integrated circuit (ASIC) …
semiconductor integrated circuits. Traditionally, application specific integrated circuit (ASIC) …
Look-up table based logic macro-cells
RU Madurawe - US Patent 7,019,557, 2006 - Google Patents
4,706,216 A 11, 1987 Carter 4,870,302 A 9, 1989 Freeman 4,873.459 A 10, 1989 El Gamal
et al. 5,343,406 A 8, 1994 Freeman et al. 5.488. 316 A 1/1996 Freeman et al. 5,844,422 A …
et al. 5,343,406 A 8, 1994 Freeman et al. 5.488. 316 A 1/1996 Freeman et al. 5,844,422 A …
Programmable structured arrays
RU Madurawe - US Patent 8,810,276, 2014 - Google Patents
BACKGROUND The present invention relates to programmable structured arrays for
semiconductor integrated circuits. Traditionally, application specific integrated circuit (ASIC) …
semiconductor integrated circuits. Traditionally, application specific integrated circuit (ASIC) …
Three dimensional programmable devices
RU Madurawe, TH White - US Patent App. 11/986,022, 2009 - Google Patents
In a first aspect, a three dimensional programmable logic device (PLD) comprises a plurality
of distributed programmable elements located in a substrate region; and a contiguous array …
of distributed programmable elements located in a substrate region; and a contiguous array …
Programmable interconnect structures and programmable integrated circuits
KE Gordon, RJ Wong - US Patent 5,701,027, 1997 - Google Patents
Antifuses and gate arrays with ann'fuses are disclosed that have high thermal stability,
reduced size. reduced leakage current. reduced capacitance in the unprogrammed state …
reduced size. reduced leakage current. reduced capacitance in the unprogrammed state …
Methods for fabricating fuse programmable three dimensional integrated circuits
RU Madurawe - US Patent 7,312,109, 2007 - Google Patents
(57) ABSTRACT A method of fabricating a field programmable integrated circuit comprised
of constructing a semiconductor device comprising a fuse circuit to customize the logic …
of constructing a semiconductor device comprising a fuse circuit to customize the logic …
Automated metal pattern generation for integrated circuits
RU Madurawe, TH White - US Patent 9,087,169, 2015 - Google Patents
An integrated circuit fabricated by a mask set including a mask to generate a metal pattern
defined by CAD software, the metal pattern generation method including: reading a binary …
defined by CAD software, the metal pattern generation method including: reading a binary …
Three dimensional integrated circuits
RU Madurawe - US Patent 7,446,563, 2008 - Google Patents
(57) ABSTRACT A programmable integrated circuit (IC), Wherein: a program mable logic
circuit is programmed to a user speci? cation by con? guring a transistor gate control signal …
circuit is programmed to a user speci? cation by con? guring a transistor gate control signal …
Semiconductor devices fabricated with different processing options
RU Madurawe - US Patent 7,759,705, 2010 - Google Patents
A semiconductor device, wherein: a first fabricating option provides a plurality of user
configurations to configure the device functionality; and a second fabricating option hard …
configurations to configure the device functionality; and a second fabricating option hard …