Online implementation of servo controllers using bit-streams

ND Patel, SK Nguang, GG Coghill… - TENCON 2005-2005 …, 2005 - ieeexplore.ieee.org
The present study proposes an alternate strategy for implementing controllers based on bit-
streams. The key to the success of bit-stream controllers is their ability to represent …

On ontology-based diagnosis and defeasibility

N Obeid, E Rawashdeh, E Alduweib… - 2016 International …, 2016 - ieeexplore.ieee.org
We aim in this paper to integrate a nonmonotonic rule system (defeasible logic) with
description logic-based ontologies. This can help us in building defeasible medical …

Field-programmable VLSI based on a bit-serial fine-grain architecture

M Hariyama, W Chong… - IEICE transactions on …, 2004 - search.ieice.org
This paper presents a novel architecture to solve two problems of existing FPGAs: the large
delay and area due to complex programmable switch blocks, and the large area due to …

Digital realization of analogue computing elements using bit streams

N Patel, G Coghill, SK Nguang - … on System-on-Chip for Real …, 2003 - ieeexplore.ieee.org
Real-time execution of an algorithm can be achieved with a fast serial processor or with a
parallel machine. Usually both of these methods use multi-bit binary words which are …

Bit streams: an alternative approach to digital controller implementation

N Patel, G Coghill, SK Nguang - Proceedings of 2003 IEEE …, 2003 - ieeexplore.ieee.org
In a digital controller, a multi-bit binary word is produced at regular intervals, which an
arithmetic unit uses to generate a new control word for the next sampling interval. This paper …

[PDF][PDF] Reconfigurable 1-bit processor array with reduced wiring area

N Nakai - 2005 - naist.repo.nii.ac.jp
Semiconductor makers have a problem of how to reduce the production cost. The production
cost is increasing because the increasing logic gates to implement and shortening …

AC compiler for implementing FPGA based bit-serial DSP systems

D Cyca, LE Turner - 2006 IEEE International Conference on …, 2006 - ieeexplore.ieee.org
This paper describes the implementation and application of a compiler used to generate
FPGA based bit-serial DSP system designs using a subset of the C programming language …

A Digit-Serial Reconfigurable VLSI Based on Quaternary Inter-Cell Data Transfer Scheme.

X Bai, N Okada, M Kameyama - Journal of Multiple-Valued …, 2013 - search.ebscohost.com
A high-throughput reconfigurable VLSI using a digit-serial architecture is proposed, where
two-bit data for each operand enters a cell per clock cycle. The interconnection complexity …

ビットシリアル演算を導入した再構成型プロセッサにおける再構成部の性能評価

谷川一哉, 梅田賢一, 弘中哲夫 - 電子情報通信学会論文誌 D, 2009 - search.ieice.org
再構成型プロセッサは適宜再構成することにより, ハードウェア資源を効率良く利用することができる
プロセッサである. しかし, 連続した処理が複数の再構成情報に分割された場合 …

Logic-In-Control-Architecture-Based Reconfigurable VLSI Using Multiple-Valued Differential-Pair Circuits

N Okada, M Kameyama - IEICE TRANSACTIONS on Information …, 2010 - search.ieice.org
A fine-grain bit-serial multiple-valued reconfigurable VLSI based on logic-in-control
architecture is proposed for effective use of the hardware resources. In logic-in-control …