The scaling of microchip technologies has enabled large scale systems-on-chip (SoC).
Network-on-chip (NoC) research addresses global communication in SoC, involving (i) a …

An asynchronous design paradigm is capable of addressing the impact of increased
process variability, power and thermal bottlenecks, high fault rates, aging, and scalability …

The modelling of large systems of spiking neurons is computationally very demanding in
terms of processing power and communication. SpiNNaker-Spiking Neural Network …

We define Quality of Service (QoS) and cost model for communications in Systems on Chip
(SoC), and derive related Network on Chip (NoC) architecture and design process. SoC …

Over the past decade, system-on-chip (SoC) designs have evolved to address the ever
increasing complexity of applications, fueled by the era of digital convergence …

A method is presented to recover 3D scene structure and camera motion from multiple
images without the need for correspondence information. The problem is framed as finding …

Managing the complexity of designing chips containing billions of transistors requires
decoupling computation from communication. For the communication, scalable and …

This invention relates to the domain of Networks on Chips (NoC). It relates to a method of
transferring data in a network on chip, particularly using an asynchronous' send/accept type …

The demands of scalable, low latency and power efficient system-on-chip interconnect
cannot only be satisfied by point-to-point or shared-bus interconnects. In this paper, we …

Single-clocked digital systems are largely a thing of the past. Although most digital circuits
remain synchronous, many designs feature multiple clock domains, often running at different …