The future transistors

W Cao, H Bu, M Vinet, M Cao, S Takagi, S Hwang… - Nature, 2023 - nature.com
The metal–oxide–semiconductor field-effect transistor (MOSFET), a core element of
complementary metal–oxide–semiconductor (CMOS) technology, represents one of the …

New structure transistors for advanced technology node CMOS ICs

Q Zhang, Y Zhang, Y Luo, H Yin - National Science Review, 2024 - academic.oup.com
Over recent decades, advancements in complementary metal-oxide-semiconductor
integrated circuits (ICs) have mainly relied on structural innovations in transistors. From …

[HTML][HTML] State of the art and future perspectives in advanced CMOS technology

HH Radamson, H Zhu, Z Wu, X He, H Lin, J Liu… - Nanomaterials, 2020 - mdpi.com
The international technology roadmap of semiconductors (ITRS) is approaching the
historical end point and we observe that the semiconductor industry is driving …

Challenges and limitations of CMOS scaling for FinFET and beyond architectures

A Razavieh, P Zeitzoff, EJ Nowak - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
Scaling trends of FinFET architecture, with focus on Front-End-of-Line (FEOL), and Middle-of-
Line (MOL) device parameters, is systematically investigated. It is concluded that the …

[HTML][HTML] A review of the gate-all-around nanosheet FET process opportunities

S Mukesh, J Zhang - Electronics, 2022 - mdpi.com
In this paper, the innovations in device design of the gate-all-around (GAA) nanosheet FET
are reviewed. These innovations span enablement of multiple threshold voltages and …

Understanding energy efficiency benefits of carbon nanotube field-effect transistors for digital VLSI

G Hills, MG Bardon, G Doornbos… - IEEE Transactions …, 2018 - ieeexplore.ieee.org
Carbon Nanotube Field-Effect Transistors (CNFETs) are highly promising to improve the
energy efficiency of digital logic circuits. Here, we quantify the Very-Large-Scale Integrated …

[HTML][HTML] Miniaturization of CMOS

HH Radamson, X He, Q Zhang, J Liu, H Cui, J **ang… - Micromachines, 2019 - mdpi.com
When the international technology roadmap of semiconductors (ITRS) started almost five
decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) …

Vertically stacked gate-all-around Si nanowire CMOS transistors with dual work function metal gates

H Mertens, R Ritzenthaler, A Chasin… - 2016 IEEE …, 2016 - ieeexplore.ieee.org
We report on the CMOS integration of vertically stacked gate-all-around (GAA) silicon
nanowire MOSFETs, with matched threshold voltages (V t, sat~ 0.35 V) for N-and P-type …

Vertically stacked gate-all-around Si nanowire transistors: Key process optimizations and ring oscillator demonstration

H Mertens, R Ritzenthaler, V Pena… - 2017 IEEE …, 2017 - ieeexplore.ieee.org
We report on CMOS-integrated vertically stacked gate-all-around (GAA) Si nanowire (NW)
MOSFETs with in-situ doped source-drain stressors and dual work function metal gates. We …

Nanowire & nanosheet FETs for ultra-scaled, high-density logic and memory applications

A Veloso, T Huynh-Bao, P Matagne, D Jang… - Solid-State …, 2020 - Elsevier
We report on vertically stacked lateral nanowires (NW)/nanosheets (NS) gate-all-around
(GAA) FET devices as promising candidates to obtain a better power-performance metric for …