Modern processors raise a challenge for WCET estimation, since detailed knowledge of the
processor microarchitecture is not available. This paper proposes a novel hybrid WCET …

Modern latency-sensitive and real-time systems often use multi-core platforms; thus, tasks
on different cores share certain hardware resources, such as the memory bus and certain …

High-performance embedded platforms are increasingly adopting heterogeneous systems-
on-chip (HeSoC) that couple multi-core CPUs with accelerators such as GPU, FPGA, or AI …

The development of multicore-based embedded real-time systems is a complex process that
encompasses several phases. During the software design and development phases (DDP) …

Due to the low costs and energy needed, cyber-physical systems are adopting multi-core
processors for their embedded computing requirements. In order to guarantee safety when …

Hardware resources found in modern processor architecture, such as the memory hierarchy,
can improve the performance of a task by anticipating its needs based on its execution …

Real-time operating systems employ spatial and temporal isolation to guarantee
predictability and schedulability of real-time systems on multi-core processors. Any …

To improve system resource utilization, multiple operators are co-located in the distributed
stream processing systems. In the colocation scenarios, the node runtime environment and …

The purpose of this paper is to describe a set of DDR3 SDRAM interference estimation cost
functions. The arbitration system of the SDRAM controller heavily impact the interference …

The emergence of a private initiative space industry has generated a race to deploy low-cost
satellites. This race translates into a strong need to reduce the manufacturing costs of a …