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Methods for do** fin field-effect transistors
CH Tsai, YL Huang, YU De-Wei - US Patent 9,209,280, 2015 - Google Patents
(57) ABSTRACT A method of do** a FinFET includes forming a semicon ductor fin on a
Substrate, the Substrate having a first device region and a second device region. The …
Substrate, the Substrate having a first device region and a second device region. The …
FinFET and method of fabricating the same
HT Lin, CY Fu, S Huang, ST Yang, HM Chen - US Patent 8,440,517, 2013 - Google Patents
The disclosure relates to a? n? eld effect transistor (FinFET). An exemplary structure for a
FinFET comprises a substrate comprising a top surface; a? rst insulation region and a sec …
FinFET comprises a substrate comprising a top surface; a? rst insulation region and a sec …
Method for fabricating a strained structure
TL Lee, CH Chang, CH Ko, F Yuan, JJ Xu - US Patent 8,497,528, 2013 - Google Patents
(57) ABSTRACT A structure for a field effect transistor on a substrate that includes a gate
Stack, an isolation structure and a source/drain (S/D) recess cavity below the top surface of …
Stack, an isolation structure and a source/drain (S/D) recess cavity below the top surface of …
Accumulation type FinFET, circuits and fabrication method thereof
CC Yeh, CS Chang, CH Wann - US Patent 8,264,032, 2012 - Google Patents
BACKGROUND As the integrated circuit size is reduced, there were efforts to overcome
problems faced with such size reduction. For example, the performance of a MOSFET is …
problems faced with such size reduction. For example, the performance of a MOSFET is …
Finfets and methods for forming the same
LS Lai, TM Kwok, CC Yeh, CH Wann - US Patent 8,264,021, 2012 - Google Patents
A Fin field effect transistor (FinFET) includes a fin-channel body over a substrate. A gate
electrode is disposed over the fin-channel body. At least one source/drain (S/D) region is …
electrode is disposed over the fin-channel body. At least one source/drain (S/D) region is …
Transistor having notched fin structure and method of making the same
CH Tseng, DW Lin, C Chien-Tai, CP Lin… - US Patent …, 2014 - Google Patents
6,858.478 B2 2/2005 Chaletal. 2005/0170593 A1 8/2005 Kang et al. 6872, 647 B1 3/2005
Yet al. 2005/0212080 A1 9, 2005 Wu et al. 6,940,747 B1 92005 Sharma et al …
Yet al. 2005/0212080 A1 9, 2005 Wu et al. 6,940,747 B1 92005 Sharma et al …
Static RAM cell design and multi-contact regime for connecting double channel transistors
F Wirbeleit - US Patent 8,183,096, 2012 - Google Patents
(57) ABSTRACT A static RAM cell may be formed on the basis of two double channel
transistors and a select transistor, wherein a body contact may be positioned laterally …
transistors and a select transistor, wherein a body contact may be positioned laterally …
Lower parasitic capacitance FinFET
CH Huang, CP Lin - US Patent 8,362,572, 2013 - Google Patents
An integrated circuit device includes a gate region extending above a semiconductor
substrate and extending in a first longitudinal direction. A first fin has a first sidewall that …
substrate and extending in a first longitudinal direction. A first fin has a first sidewall that …
Self-aligned fin transistor formed on a bulk substrate by late fin etch
T Scheiper, A Wei - US Patent 8,722,498, 2014 - Google Patents
Non-planar transistors, such as FinFETs, may be formed in a bulk configuration in the
context of a replacement gate approach, wherein the semiconductor fins are formed during …
context of a replacement gate approach, wherein the semiconductor fins are formed during …
Method for forming high germanium concentration SiGe stressor
CH Chang, JJ Xu, CH Wang, CC Yeh… - US Patent …, 2014 - Google Patents
A method for producing a SiGe stressor with high Ge concentration is provided. The method
includes providing a semiconductor substrate with a source area, a drain area, and a …
includes providing a semiconductor substrate with a source area, a drain area, and a …