Power measurement methodology for FPGA devices
R Jevtic, C Carreras - IEEE Transactions on Instrumentation …, 2010 - ieeexplore.ieee.org
The efficiency of power optimization tools depends on information on design power provided
by the power estimation models. Power models targeting different power groups can enable …
by the power estimation models. Power models targeting different power groups can enable …
Power estimation of embedded multiplier blocks in FPGAs
R Jevtic, C Carreras - IEEE transactions on Very large scale …, 2009 - ieeexplore.ieee.org
The use of embedded multiplier blocks has become a norm in DSP applications due to their
high performance and low power consumption. However, as their implementation details in …
high performance and low power consumption. However, as their implementation details in …
Tracking the pipelining-power rule along the FPGA technical literature
This work reviews the contributions of power-oriented pipelining over the last two decades,
and adds up-to-date results on 65 nm and 45 nm FPGAs. The data show that power …
and adds up-to-date results on 65 nm and 45 nm FPGAs. The data show that power …
Power estimation of dividers implemented in FPGAs
We present a methodology for power estimation of non-fractional divider cores implemented
in FPGAs. The methodology takes into account the divider structure and the signal statistics …
in FPGAs. The methodology takes into account the divider structure and the signal statistics …
[HTML][HTML] Accurate dynamic power estimation for CMOS combinational logic circuits with real gate delay model
Dynamic power estimation is essential in designing VLSI circuits where many parameters
are involved but the only circuit parameter that is related to the circuit operation is the nodes' …
are involved but the only circuit parameter that is related to the circuit operation is the nodes' …
Wordlength optimization of fixed-point algorithms
G Caffarena - … Techniques: From Component-to Application-Level, 2022 - Springer
Approximate computing enables trading off accuracy with implementation cost for
embedded implementations of algorithms. Wordlength optimization provides a means to …
embedded implementations of algorithms. Wordlength optimization provides a means to …
IP characterization methodology for fast and accurate power consumption estimation at transactional level model
M Rogers-Vallée, MA Cantin, L Moss… - 2010 IEEE International …, 2010 - ieeexplore.ieee.org
Estimating the power consumption of System on Chip as early as possible in the design life
cycle is important to meet the time to market requirements. For this purpose, most research is …
cycle is important to meet the time to market requirements. For this purpose, most research is …
Power efficient implementation of bit-parallel unrolled CORDIC structures for FPGA platforms
Power consumption is one of the major concerns while map** designs on FPGAs.
Dynamic power dissipation in FPGAs is a strong function of the switching activity of the …
Dynamic power dissipation in FPGAs is a strong function of the switching activity of the …
Triple-bit method for power estimation of nonlinear digital circuits in FPGAs
Power consumption of many of the digital signal processing systems available is nonlinear.
Signal distribution at the multiplier output changes significantly with respect to its input signal …
Signal distribution at the multiplier output changes significantly with respect to its input signal …
[PDF][PDF] High-Level Power Estimation of DSP Circuits Implemented in FPGAs
R Jevtic - Universidad Politécnica de Madrid, 2009 - die.upm.es
Power consumption in microelectronic devices and circuits has become a critical design
concern in recent years due to the rapid growth of personal wireless communications …
concern in recent years due to the rapid growth of personal wireless communications …