Verifying large multipliers by combining SAT and computer algebra
We combine SAT and computer algebra to substantially improve the most effective approach
for automatically verifying integer multipliers. In our approach complex final stage adders are …
for automatically verifying integer multipliers. In our approach complex final stage adders are …
RevSCA-2.0: SCA-based formal verification of nontrivial multipliers using reverse engineering and local vanishing removal
The formal verification of integer multipliers is one of the important but challenging problems
in the verification community. Recently, the methods based on symbolic computer algebra …
in the verification community. Recently, the methods based on symbolic computer algebra …
Towards formal verification of optimized and industrial multipliers
Formal verification methods have made huge progress over the last decades. However,
proving the correctness of arithmetic circuits involving integer multipliers still drives the …
proving the correctness of arithmetic circuits involving integer multipliers still drives the …
Late breaking results: Polynomial formal verification of fast adders
Despite the recent success of formal verification methods, the computational complexity of
most of them is still unknown. It raises serious questions regarding the scalability of the …
most of them is still unknown. It raises serious questions regarding the scalability of the …
Gamora: Graph learning based symbolic reasoning for large-scale boolean networks
Reasoning high-level abstractions from bit-blasted Boolean networks (BNs) such as gate-
level netlists can significantly benefit functional verification, logic minimization, datapath …
level netlists can significantly benefit functional verification, logic minimization, datapath …
Polynomial word-level verification of arithmetic circuits
Verifying the functional correctness of a circuit is often the most time-consuming part of the
design process. Recently, world-level formal verification methods, eg, Binary Moment …
design process. Recently, world-level formal verification methods, eg, Binary Moment …
Graph learning-based arithmetic block identification
Arithmetic block identification in gate-level netlist is an essential procedure for malicious
logic detection, functional verification, or macro-block optimization. We argue that existing …
logic detection, functional verification, or macro-block optimization. We argue that existing …
Polynomial formal verification of arithmetic circuits
The size and the complexity of digital circuits are increasing rapidly. This makes the circuits
highly error-prone. As a result, proving the correctness of a circuit is of utmost importance …
highly error-prone. As a result, proving the correctness of a circuit is of utmost importance …
Survey of machine learning for software-assisted hardware design verification: Past, present, and prospect
With the ever-increasing hardware design complexity comes the realization that efforts
required for hardware verification increase at an even faster rate. Driven by the push from …
required for hardware verification increase at an even faster rate. Driven by the push from …
AMulet 2.0 for Verifying Multiplier Circuits
AMulet 2.0 is a fully automatic tool for the verification of integer multipliers using computer
algebra. Our tool models multiplier circuits given as and-inverter graphs as a set of …
algebra. Our tool models multiplier circuits given as and-inverter graphs as a set of …