Verifying large multipliers by combining SAT and computer algebra

D Kaufmann, A Biere, M Kauers - 2019 Formal Methods in …, 2019 - ieeexplore.ieee.org
We combine SAT and computer algebra to substantially improve the most effective approach
for automatically verifying integer multipliers. In our approach complex final stage adders are …

RevSCA-2.0: SCA-based formal verification of nontrivial multipliers using reverse engineering and local vanishing removal

A Mahzoon, D Große… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
The formal verification of integer multipliers is one of the important but challenging problems
in the verification community. Recently, the methods based on symbolic computer algebra …

Towards formal verification of optimized and industrial multipliers

A Mahzoon, D Große, C Scholl… - … Design, Automation & …, 2020 - ieeexplore.ieee.org
Formal verification methods have made huge progress over the last decades. However,
proving the correctness of arithmetic circuits involving integer multipliers still drives the …

Late breaking results: Polynomial formal verification of fast adders

A Mahzoon, R Drechsler - 2021 58th ACM/IEEE Design …, 2021 - ieeexplore.ieee.org
Despite the recent success of formal verification methods, the computational complexity of
most of them is still unknown. It raises serious questions regarding the scalability of the …

Gamora: Graph learning based symbolic reasoning for large-scale boolean networks

N Wu, Y Li, C Hao, S Dai, C Yu… - 2023 60th ACM/IEEE …, 2023 - ieeexplore.ieee.org
Reasoning high-level abstractions from bit-blasted Boolean networks (BNs) such as gate-
level netlists can significantly benefit functional verification, logic minimization, datapath …

Polynomial word-level verification of arithmetic circuits

M Barhoush, A Mahzoon, R Drechsler - Proceedings of the 19th ACM …, 2021 - dl.acm.org
Verifying the functional correctness of a circuit is often the most time-consuming part of the
design process. Recently, world-level formal verification methods, eg, Binary Moment …

Graph learning-based arithmetic block identification

Z He, Z Wang, C Bai, H Yang… - 2021 IEEE/ACM …, 2021 - ieeexplore.ieee.org
Arithmetic block identification in gate-level netlist is an essential procedure for malicious
logic detection, functional verification, or macro-block optimization. We argue that existing …

Polynomial formal verification of arithmetic circuits

R Drechsler, A Mahzoon, L Weingarten - Proceedings of International …, 2022 - Springer
The size and the complexity of digital circuits are increasing rapidly. This makes the circuits
highly error-prone. As a result, proving the correctness of a circuit is of utmost importance …

Survey of machine learning for software-assisted hardware design verification: Past, present, and prospect

N Wu, Y Li, H Yang, H Chen, S Dai, C Hao… - ACM Transactions on …, 2024 - dl.acm.org
With the ever-increasing hardware design complexity comes the realization that efforts
required for hardware verification increase at an even faster rate. Driven by the push from …

AMulet 2.0 for Verifying Multiplier Circuits

D Kaufmann, A Biere - International Conference on Tools and Algorithms …, 2021 - Springer
AMulet 2.0 is a fully automatic tool for the verification of integer multipliers using computer
algebra. Our tool models multiplier circuits given as and-inverter graphs as a set of …