ZyPR: end-to-end build tool and runtime manager for partial reconfiguration of FPGA SoCs at the edge

AR Bucknall, SA Fahmy - ACM Transactions on Reconfigurable …, 2023 - dl.acm.org
Partial reconfiguration (PR) is a key enabler to the design and development of adaptive
systems on modern Field Programmable Gate Array (FPGA) Systems-on-Chip (SoCs) …

Automated Generation and Orchestration of Stream Processing Pipelines on FPGAs

K Mätas, K Manev, J Powell… - … Conference on Field …, 2022 - ieeexplore.ieee.org
FPGAs have demonstrated substantial performance and energy efficiency advantages for
workloads that fit a stream processing model with direct module-to-module communication …

Rhlab: Towards implementing a partial reconfigurable sdr remote lab

Z Zhang, M Inoñan, P Orduña, R Hussein - International Conference on …, 2024 - Springer
Abstract Software-Defined Radio (SDR) remote labs permit students to experiment with real
wireless communication, designing Radio Frequency (RF) systems with minimal code …

Cross-Chip Partial Reconfiguration for the Initialisation of Modular and Scalable Heterogeneous Systems

M Fuchs, H Krause, T Muscheid… - … on Nuclear Science, 2024 - ieeexplore.ieee.org
The almost unlimited possibilities to customize the logic in an FPGA are one of the main
reasons for the versatility of these devices. Partial reconfiguration exploits this capability …

[ΒΙΒΛΙΟ][B] Resource Elastic Dynamic Stream Processing on FPGAs Exemplified on Database Acceleration

KN Manev - 2022 - search.proquest.com
While FPGAs are becoming mainstream in the deployment of datacenters and cloud
systems, they are mostly used as updatable ASICs. This thesis shows that it is feasible to …

Runtime Management of Dynamic Dataflows with Partially Reconfigurable Pipelines on FPGAs

K Mätas - 2023 - search.proquest.com
In order to overcome the famous von Neumann bottleneck, FPGAs employ a dataflow model
that processes data through a pipeline of operator modules, akin to an assembly line for …