Pf-dram: a precharge-free dram structure

N Rohbani, S Darabi… - 2021 ACM/IEEE 48th …, 2021 - ieeexplore.ieee.org
Although DRAM capacity and bandwidth have increased sharply by the advances in
technology and standards, its latency and energy per access have remained almost …

Traffic steering between a low-latency unswitched TL ring and a high-throughput switched on-chip interconnect

J Oh, A Zajic, M Prvulovic - Proceedings of the 22nd …, 2013 - ieeexplore.ieee.org
Growth in core count creates an increasing demand for interconnect bandwidth, driving a
change from shared buses to packet-switched on-chip interconnects. However, this …

Logical memory buffers for a media controller

MR Krause - US Patent 10,509,742, 2019 - Google Patents
In some examples, a media controller includes a buffer and controller circuitry. The controller
circuitry may receive, from a memory device linked to the media controller, an indication of a …

Resha** cache misses to improve row-buffer locality in multicore systems

W Ding, J Liu, M Kandemir… - Proceedings of the 22nd …, 2013 - ieeexplore.ieee.org
Optimizing cache locality has always been important since the emergence of caches, and
numerous cache locality optimization schemes have been published in compiler literature …

[КНИГА][B] Bundling Spatially Correlated Prefetches for Improved Main Memory Row Buffer Locality

P Judd - 2014 - search.proquest.com
Row buffer locality is a consequence of programs' inherent spatial locality that the memory
system can easily exploit for significant performance gains and power savings. However, as …

A Fresh Look At Data Locality On Emerging Multicores And Manycores

W Ding - 2014 - etda.libraries.psu.edu
The emergence of multicore platforms offers several opportunities for boosting ap-plication
performance. These opportunities, which include parallelism and data locality benefits …