Image preprocessing for generalized image processing
E Delaye, A Sirasao, A Ng, Y Wu, J Zejda - US Patent 11,386,644, 2022 - Google Patents
An example preprocessor circuit includes: a first buffer configured to store rows of image
data and output a row thereof; a second buffer, coupled to the first buffer, including storage …
data and output a row thereof; a second buffer, coupled to the first buffer, including storage …
Convolutional neural network on programmable two dimensional image processor
(57) ABSTRACT A method is described that includes executing a convolu tional neural
network layer on an image processor having an array of execution lanes and a two …
network layer on an image processor having an array of execution lanes and a two …
Deep vision processor
W Qadeer, R Hameed - US Patent 10,474,464, 2019 - Google Patents
Disclosed herein is a processor for deep learning. In one embodiment, the processor
comprises: a load and store unit configured to load and store image pixel data and stencil …
comprises: a load and store unit configured to load and store image pixel data and stencil …
Statistics operations on two dimensional image processor
E Chang, DF Finchelstein, SR Hung… - US Patent …, 2021 - Google Patents
(57) ABSTRACT A method is described that includes loading an array of content into a two-
dimensional shift register. The two dimensional shift register is coupled to an execution lane …
dimensional shift register. The two dimensional shift register is coupled to an execution lane …
Convolutional neural network on programmable two dimensional image processor
A method is described that includes executing a convolutional neural network layer on an
image processor having an array of execution lanes and a two-dimensional shift register …
image processor having an array of execution lanes and a two-dimensional shift register …
Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register
A method is described that includes, on an image processor having a two dimensional
execution lane array and a two dimensional shift register array, repeatedly shifting first …
execution lane array and a two dimensional shift register array, repeatedly shifting first …
Compiler managed memory for image processor
(57) ABSTRACT A method is described. The method includes repeatedly loading a next
sheet of image data from a first location of a memory into a two dimensional shift register …
sheet of image data from a first location of a memory into a two dimensional shift register …
Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register
A method is described that includes, on an image processor having a two dimensional
execution lane array and a two dimensional shift register array, repeatedly shifting first …
execution lane array and a two dimensional shift register array, repeatedly shifting first …
Line buffer unit for image processor
An apparatus is described that include a line buffer unit composed of a plurality of a line
buffer interface units. Each line buffer interface unit is to handle one or more requests by a …
buffer interface units. Each line buffer interface unit is to handle one or more requests by a …
Compiler managed memory for image processor
A method is described. The method includes repeatedly loading a next sheet of image data
from a first location of a memory into a two dimensional shift register array. The memory is …
from a first location of a memory into a two dimensional shift register array. The memory is …