Transient temperature distribution in a multilayer semiconductor device with dynamic thermal load and non-uniform thermal contact resistance between layers
The thermal management challenge in microelectronic chips is exacerbated by their
multilayer architecture and manufacturing processes that introduce non-uniform thermal …
multilayer architecture and manufacturing processes that introduce non-uniform thermal …
An explicit analytical model for rapid computation of temperature field in a three-dimensional integrated circuit (3D IC)
L Choobineh, A Jain - International Journal of Thermal Sciences, 2015 - Elsevier
Abstract 3D integrated circuits (3-D ICs) technology is a promising approach for next-
generation semiconductor microelectronics. A 3D IC is formed by vertical interconnection of …
generation semiconductor microelectronics. A 3D IC is formed by vertical interconnection of …
Thermal evaluation of 2.5-D integration using bridge-chip technology: Challenges and opportunities
In this paper, 2.5-D integrated circuits (ICs) using bridge-chip technology are thermally
evaluated to investigate thermal challenges and opportunities for such multi-die packages …
evaluated to investigate thermal challenges and opportunities for such multi-die packages …
Compact lateral thermal resistance model of TSVs for fast finite-difference based thermal analysis of 3-D stacked ICs
Thermal issue is the leading design constraint for 3-D stacked integrated circuits (ICs) and
through silicon vias (TSVs) are used to effectively reduce the temperature of 3-D ICs …
through silicon vias (TSVs) are used to effectively reduce the temperature of 3-D ICs …
An analytical placement framework for 3-D ICs and its extension on thermal awareness
In this paper, we present a high-quality analytical 3-D placement framework. We propose
using a Huber-based local smoothing technique to work with a Helmholtz-based global …
using a Huber-based local smoothing technique to work with a Helmholtz-based global …
A High-Efficiency Design Method of TSV Array for Thermal Management of 3-D Integrated System
In this article, a high-efficient design method of through silicon via (TSV) array for thermal
management of 3-dimensional (3-D) integrated system is developed based on the …
management of 3-dimensional (3-D) integrated system is developed based on the …
Online fault tolerance technique for TSV-based 3-D-IC
Y Zhao, S Khursheed… - IEEE Transactions on Very …, 2014 - ieeexplore.ieee.org
This brief presents the design, validation, and evaluation of an efficient online fault tolerance
technique for fault detection and recovery in presence of three through-silicon-vias (TSV) …
technique for fault detection and recovery in presence of three through-silicon-vias (TSV) …
An analytical through silicon via (TSV) surface roughness model applied to a millimeter wave 3-D IC
In the millimeter wave (mmW) frequency range, the root mean square height of the through
silicon via (TSV) sidewall roughness is comparable to the skin depth, and hence, becomes a …
silicon via (TSV) sidewall roughness is comparable to the skin depth, and hence, becomes a …
Tenacious hardware trojans due to high temperature in middle tiers of 3-D ICs
Hardware security is a major concern in the intellectual property (IP) centric integrated
circuits (IC). 3-D IC design augments IP centric designs. However, 3-D ICs suffer from high …
circuits (IC). 3-D IC design augments IP centric designs. However, 3-D ICs suffer from high …
An analytical model for steady-state and transient temperature fields in 3-D integrated circuits
K Wang, Z Pan - IEEE Transactions on Components, Packaging …, 2016 - ieeexplore.ieee.org
This paper proposes a noniterative analytical thermal model for 3-D integrated circuits (3-D-
ICs) based on the solution of the governing energy equations using Green's function …
ICs) based on the solution of the governing energy equations using Green's function …