An analysis on power consumption and performance in runtime hardware reconfiguration

DS Loubach - International Journal of Embedded Systems, 2021 - inderscienceonline.com
It will be more difficult to continue with Moore's law scaling in the next years without
exploring new heterogeneous architectures with application-customised hardware. The …

Translating timing into an architecture: the synergy of COTSon and HLS (domain expertise—designing a computer architecture via HLS)

R Giorgi, F Khalili, M Procaccini - International Journal of …, 2019 - Wiley Online Library
Translating a system requirement into a low‐level representation (eg, register transfer level
or RTL) is the typical goal of the design of FPGA‐based systems. However, the Design …

A runtime reconfiguration design targeting avionics systems

DS Loubach - 2016 IEEE/AIAA 35th Digital Avionics Systems …, 2016 - ieeexplore.ieee.org
Real-time embedded systems are present in various application domains such as
automotive, aeronautical, space, and telecommunications. Avionics systems (ie, aviation …

System-level design space identification for Many-Core Vision Processors

J Yudi, CH Llanos, M Huebner - Microprocessors and Microsystems, 2017 - Elsevier
The current main trends in the embedded systems area, the Cyber-Physical Systems (CPS)
and the Internet-of-Things (IoT), are leveraging the development of complex, distributed, low …

Future trends on adaptive processing systems

B Janßen, JY Mori, O Navarro… - … on Parallel and …, 2014 - ieeexplore.ieee.org
Today ubiquitous computing is steadily growing in daily life, leading to an increasing need of
resource awareness especially for devices with limited energy source. The running …

A new concept for system-level design of runtime reconfigurable real-time systems

A Luppold, B Menhorn, H Falk, F Slomka - ACM SIGBED Review, 2013 - dl.acm.org
This concept paper proposes a new system-level design methodology for runtime
reconfigurable adaptive heterogeneous systems in a real-time environment. Today, among …

[PDF][PDF] A Data-Flow Threads Co-Processor for MPSoC FPGA Clusters

FK Maybodi - 2021 - flore.unifi.it
Abstract Data-Flow Threads (DF-Threads) is an execution model previously proposed by R.
Giorgi [1] that distributes many asynchronous parallel threads in a multicore multi-node …

[PDF][PDF] Towards runtime adaptivity by using models of computation for real-time embedded systems design

DS Loubach, EGO Nóbrega, I Sander… - 9th Aerospace …, 2016 - fem.unicamp.br
Towards Runtime Adaptivity by using Models of Computation for Real-Time Embedded
Systems Design Page 1 9th Aerospace Technology Congress 2016 LOUBACH, DS et al About …

Dynamic power reduction in self-adaptive embedded systems through benchmark analysis

A Scionti, S Kavvadias, R Giorgi - 2014 3rd Mediterranean …, 2014 - ieeexplore.ieee.org
Discovering the most appropriate reconfiguration instants for improving performance and
lowering power consumption is not a trivial problem. In this paper we show the benefit in …

A data-flow execution engine for scalable embedded computing

M Procaccini, R Giorgi - Acaces Poster Abstract 2017, 2017 - usiena-air.unisi.it
Nowadays embedded systems are increasingly used in the world of distributed computing to
provide more computational power without having to change the whole system and the …