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Mechanisms Limiting EOT Scaling and Gate Leakage Currents of High- /Metal Gate Stacks Directly on SiGe
J Huang, PD Kirsch, J Oh, SH Lee… - IEEE electron device …, 2009 - ieeexplore.ieee.org
This letter addresses mechanisms responsible for a high gate leakage current (Jg) and a
thick interfacial layer in the surface channel SiGe pFET enabling transistor fabrication with …
thick interfacial layer in the surface channel SiGe pFET enabling transistor fabrication with …
Intrinsic reliability improvement in biaxially strained SiGe p-MOSFETs
In this letter, we show an improvement not only in performance but also in reliability of a 30-
nm-thick biaxially strained SiGe (20% Ge) channel on Si p-type metal-oxide semiconductor …
nm-thick biaxially strained SiGe (20% Ge) channel on Si p-type metal-oxide semiconductor …
Investigation of SiGe/Si Bilayer Inverted-T Channel Gate-All-Around Field-Effect-Transistor With Self-Induced Ferroelectric Ge Doped HfO₂
CJ Sun, YJ Yao, SC Yan, YW Lin… - IEEE Journal of the …, 2022 - ieeexplore.ieee.org
We investigated the ferroelectric properties of self-induced HfGeO x in a HfO 2 film deposited
on a SiGe substrate and analyzed a novel ferroelectric inverted T channel gate-all-around …
on a SiGe substrate and analyzed a novel ferroelectric inverted T channel gate-all-around …
Enhanced hole mobility and low $ Tinv $ for pMOSFET by a novel epitaxial Si/Ge superlattice channel
CH Fu, KS Chang-Liao, LJ Liu… - IEEE electron device …, 2012 - ieeexplore.ieee.org
Since the SiGe or Ge channel materials are desirable to enhance the carrier mobility
degraded by ultrathin high-k gate dielectric, the pMOSFET device with novel superlattice …
degraded by ultrathin high-k gate dielectric, the pMOSFET device with novel superlattice …
The Improvement of High-/Metal Gate pMOSFET Performance and Reliability Using Optimized Si Cap/SiGe Channel Structure
WK Yeh, YT Chen, FS Huang, CW Hsu… - … on Device and …, 2010 - ieeexplore.ieee.org
The impact of the Si cap/SiGe layer on the Hf-based high-k/metal gate SiGe channel
pMOSFET performance and reliability has been investigated. We proposed an optimized …
pMOSFET performance and reliability has been investigated. We proposed an optimized …
Optimized design of Si-cap layer in strained-SiGe channel p-MOSFETs based on computational and experimental approaches
J Sato-Iwanaga, A Inoue, H Sorada, T Takagi… - Solid-state …, 2014 - Elsevier
In this paper, we study the hole transport properties in strained-SiGe channel p-MOSFETs
(sSG pMOSFETs) with a Si-cap layer, which is introduced to avoid degradation of interface …
(sSG pMOSFETs) with a Si-cap layer, which is introduced to avoid degradation of interface …
Correlation between interface traps and random dopants in emerging MOSFETs
YY Chiu, Y Li, HW Cheng - 2011 International Conference on …, 2011 - ieeexplore.ieee.org
In this work, we for the first time study the fluctuation and interaction between interface traps
(ITs) and random dopants (RDs) of 16 nm MOSFETs. Totally random devices with 2D ITs at …
(ITs) and random dopants (RDs) of 16 nm MOSFETs. Totally random devices with 2D ITs at …
Control of epitaxial growth of SiGe
R van Roijen, M Steigerwalt, JD Bell… - IEEE Transactions …, 2015 - ieeexplore.ieee.org
Silicon-Germanium (SiGe), used to boost pFET performance and enhance the properties of
high-metal gate devices, is grown by selective epitaxy on silicon. Since device parameters …
high-metal gate devices, is grown by selective epitaxy on silicon. Since device parameters …
[LIBRO][B] Kinetic Studies in GeO2/Ge System: A Retrospective from 2021
SK Wang - 2022 - taylorfrancis.com
Kinetic Studies in GeO2/Ge System: A Retrospective from 2021 investigates reaction kinetics
in GeO2/Ge systems, aiming to demonstrate the fundamentals of the GeO2/Ge interface and …
in GeO2/Ge systems, aiming to demonstrate the fundamentals of the GeO2/Ge interface and …
Datamining for yield
R Van Roijen, JB Maxson… - 2017 28th Annual …, 2017 - ieeexplore.ieee.org
A small but persistent signal in wafer slot order was observed at functional test, affecting
logic yield. Through wafer slot Randomization at several operations in the route a process …
logic yield. Through wafer slot Randomization at several operations in the route a process …