The adoption of aggressively down-scaled voltages along with worsening process
variations, render nanometer devices prone to timing errors that threaten system …

Nanometer circuits are becoming increasingly prone to timing errors due to worsening
parametric variations and operation close to voltage and frequency limits. Such errors …

The pursuit of miniature energy-efficient chips, and push for scaled voltages leads to
increased timing errors that threaten the correct system functionality. Conventional error …

Moore's Law is still alive and well, as far as increasing the complexity of integrated circuits
(ICs) is concerned. Logic ICs with about 20 billion transistors or even more are being …

As the timing guardband consumes more and more design margin with the technology
scaling, better-than-worst-case (BTWC) techniques have gained more attention as a …

This paper showcases the novel application of Deep-Learning (DL) in the development of
accurate microarchitecture and workload-aware timing error models and investigates …

In 1975, Moore observed that the complexity of integrated circuits would double every two
years towards the end of the decade, instead of every year [83]. He predicted that this would …

With the continuous development of the computer field, the network application is more and
more extensive, and various security problems also appear. In this environment, a self …