Timing, energy, and thermal performance of three-dimensional integrated circuits
We examine the performance of custom circuits in an emerging technology known as three-
dimensional integration. By combining multiple device layers with a high-density inter-layer …
dimensional integration. By combining multiple device layers with a high-density inter-layer …
SET-based nano-circuit simulation and design method using HSPICE
F Zhang, R Tang, YB Kim - Proceedings of the 14th ACM Great Lakes …, 2004 - dl.acm.org
This paper presents a simulation and design method for complementary SET-based nano-
circuits. A HSPICE behavioral implementation of modified Lientschnig's SET model based …
circuits. A HSPICE behavioral implementation of modified Lientschnig's SET model based …
Influence of negative metal ion bombardment on the properties of ITO/PET films deposited by dc magnetron sputtering
D Kim - Journal of non-crystalline solids, 2003 - Elsevier
Transparent conducting indium tin oxide (ITO) thin films were deposited on a polyethylene
terephthalate (PET) substrate at a low substrate temperature by dc magnetron sputtering …
terephthalate (PET) substrate at a low substrate temperature by dc magnetron sputtering …
Nanowire field effect transistor device
(57) ABSTRACT A method for forming a field effect transistor device includes forming a
nanowire Suspended above a substrate, forming a dummy gate stack on a portion of the …
nanowire Suspended above a substrate, forming a dummy gate stack on a portion of the …
A dual-gate-controlled single-electron transistor using self-aligned polysilicon sidewall spacer gates on silicon-on-insulator nanowire
SF Hu, YC Wu, CL Sung, CY Chang… - IEEE transactions on …, 2004 - ieeexplore.ieee.org
A dual-gate-controlled single-electron transistor was fabricated by using self-aligned
polysilicon sidewall spacer gates on a silicon-on-insulator nanowire. The quantum dot …
polysilicon sidewall spacer gates on a silicon-on-insulator nanowire. The quantum dot …
Influence of the Cs partial pressure on the optical and electrical properties of ITO films prepared by dc sputter type negative metal ion beam deposition
D Kim - Optical Materials, 2003 - Elsevier
The influence of cesium (Cs) partial pressure (PCs) in the sputtering atmosphere on the opto-
electrical and surface morphological property of ITO thin films deposited onto unheated …
electrical and surface morphological property of ITO thin films deposited onto unheated …
Self-aligned dual-gate single-electron transistors
A novel complementary metal–oxide–semiconductor (CMOS) process compatible and self-
aligned fabrication method for the dual-gate single-electron transistor (DG-SET) is …
aligned fabrication method for the dual-gate single-electron transistor (DG-SET) is …
Method for fabricating nano devices
Embodiments relate to a method for fabricating nano-wires in nano-devices, and more
particularly to nano-device fabrica tion using end-of-range (EOR) defects. In one …
particularly to nano-device fabrica tion using end-of-range (EOR) defects. In one …
Robust HSPICE modeling of a single electron turnstile
This paper presents a novel HSPICE circuit model for designing and simulating a single-
electron (SE) turnstile, as applicable at the nanometric feature sizes. The proposed SE …
electron (SE) turnstile, as applicable at the nanometric feature sizes. The proposed SE …
Nonlinear current-voltage characteristics of bismuth nanodot structures
PHP Chiu, I Shih - Applied physics letters, 2006 - pubs.aip.org
Bismuth (Bi) nanodot structures have been fabricated using the proximity effects of electron-
beam writing technique. Bi nanodots, each 100 nm in diameter, were fabricated on an …
beam writing technique. Bi nanodots, each 100 nm in diameter, were fabricated on an …