[PDF][PDF] Tutorial on high-level synthesis
High-level synthesis takes an abstract behavioral specification of a digital system and finds a
register-transfer level structure that realizes the given behavior. In this tutorial we will …
register-transfer level structure that realizes the given behavior. In this tutorial we will …
Loop optimization in register-transfer scheduling for DSP-systems
G Goossens, J Vandewlle, H De Man - … of the 26th ACM/IEEE Design …, 1989 - dl.acm.org
In this paper, we discuss a control-flow transformation called loop folding, during the
scheduling of register-transfer code for DSP-systems. Loop folding is functionally equivalent …
scheduling of register-transfer code for DSP-systems. Loop folding is functionally equivalent …
[BOOK][B] Structured logic design with VHDL
JR Armstrong, FG Gray - 1993 - dl.acm.org
VHDL is the Very High Speed Integrated Circuit (VHSIC) Hardware Description Language
that was standardized as ANSIIEEE standard 1076 in 1987 (this version is known as …
that was standardized as ANSIIEEE standard 1076 in 1987 (this version is known as …
[PDF][PDF] HERCULES-a System for High-Level Synthesis.
This paper presents an approach to lhigh-level synthesis of VLSl processors and systens.
Synthesis consists of two phases: beliavioral synthesis, which involves inplementation …
Synthesis consists of two phases: beliavioral synthesis, which involves inplementation …
The Princeton University behavioral synthesis system
W Wolf, A Takach, CY Huang… - … 29th ACM/IEEE …, 1992 - ieeexplore.ieee.org
The Princeton University behavioral synthesis system (PUBSS) is a high-level synthesis
system targeted to control-dominated machines. PUBSS compiles a very high-speed …
system targeted to control-dominated machines. PUBSS compiles a very high-speed …
Anatomy of a hardware compiler
Programming-language compilers generate code targeted to machines with fixed
architectures, either parallel or serial. Compiler techniques can also be used to generate the …
architectures, either parallel or serial. Compiler techniques can also be used to generate the …
A design utility manager: the ADAM planning engine
DW Knapp, AC Parker - 23rd ACM/IEEE Design Automation …, 1986 - ieeexplore.ieee.org
In this paper we present a software package which manages the digital design process
using a planning paradigm. Under this paradigm design is seen as a process in which …
using a planning paradigm. Under this paradigm design is seen as a process in which …
The ADAM design planning engine
DW Knapp, AC Parker - … on computer-aided design of integrated …, 1991 - ieeexplore.ieee.org
A novel paradigm for managing the digital process is presented. Under this paradigm,
design is seen as a process in which abstract models of design tools are applied to abstract …
design is seen as a process in which abstract models of design tools are applied to abstract …
System synthesis using behavioural descriptions
H Kramer, W Rosenstiel - Proceedings of the European Design …, 1990 - ieeexplore.ieee.org
The authors present an architectural synthesis system. The system is able to generate
multiprocessor architectures from behavioural descriptions. It combines the flexibility of so …
multiprocessor architectures from behavioural descriptions. It combines the flexibility of so …
Architectural optimization methods for control-dominated machines
W Wolf, A Takach, TC Lee - High-Level VLSI Synthesis, 1991 - Springer
We are building the Princeton University Behavioral Synthesis System (PUBSS) as a testbed
for high-level synthesis methods. Our research in high-level synthesis is guided by two …
for high-level synthesis methods. Our research in high-level synthesis is guided by two …