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Oscillator flicker phase noise: A tutorial
A deep understanding of how to reduce flicker phase noise (PN) in oscillators is critical in
supporting ultra-low PN frequency generation for the advanced communications and other …
supporting ultra-low PN frequency generation for the advanced communications and other …
Low-jitter frequency generation techniques for 5G communication: A tutorial
W Wu - IEEE Solid-State Circuits Magazine, 2021 - ieeexplore.ieee.org
5G is the latest global wireless standard, known as the fifth generation of cellular mobile
communication technology. Compared to 4G LTE, 5G increases peak data rates and …
communication technology. Compared to 4G LTE, 5G increases peak data rates and …
A low-phase-noise quad-core millimeter-wave fundamental VCO using circular triple-coupled transformer in 65-nm CMOS
The minimal achievable phase noise (PN) of millimeter-wave (mm-wave) voltage-controlled
oscillators (VCOs) is bounded by the smallest realizable inductor with a reasonable high …
oscillators (VCOs) is bounded by the smallest realizable inductor with a reasonable high …
A fully integrated 0.27-THz injection-locked frequency synthesizer with frequency-tracking loop in 65-nm CMOS
A fully integrated sub-terahertz (sub-THz) frequency synthesizer is proposed cascading a
radio frequency subsampling phase-locked loop (SS-PLL) with millimeter-wave injection …
radio frequency subsampling phase-locked loop (SS-PLL) with millimeter-wave injection …
17.6 A 21.7-to-26.5 GHz charge-sharing locking quadrature PLL with implicit digital frequency-tracking loop achieving 75fs jitter and− 250dB FoM
Sub-sampling (SS) and injection-locking (IL) techniques are becoming increasingly popular
for 5G millimeter-wave (mmW) frequency generation [1],[2] due to their ability to achieve ultra …
for 5G millimeter-wave (mmW) frequency generation [1],[2] due to their ability to achieve ultra …
A charge-sharing locking technique with a general phase noise theory of injection locking
This article presents a millimeter-wave (mmW) frequency synthesizer based on a new
charge-sharing locking (CSL) technique. A charge-preset capacitor is introduced for charge …
charge-sharing locking (CSL) technique. A charge-preset capacitor is introduced for charge …
Design and analysis of 55–63-GHz fundamental quad-core VCO with NMOS-only stacked oscillator in 28-nm CMOS
This article presents a 55–63-GHz fundamental multicore voltage-controlled oscillator (VCO)
in a 28-nm bulk CMOS process. The single-core VCO utilizes stacking and magnetic …
in a 28-nm bulk CMOS process. The single-core VCO utilizes stacking and magnetic …
A 31- W, 148-fs Step, 9-bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28-nm CMOS
This article proposes a power-efficient highly linear capacitor-array-based digital-to-time
converter (DTC) using a charge redistribution constant-slope approach. A fringe-capacitor …
converter (DTC) using a charge redistribution constant-slope approach. A fringe-capacitor …
A 529-μW fractional-N all-digital PLL using TDC gain auto-calibration and an inverse-class-F DCO in 65-nm CMOS
This paper presents an ultra-lower-power (ULP) digital-to-time-converter (DTC)-assisted
fractional-N all-digital phase-locked loop (ADPLL) suitable for IoT applications. A proposed …
fractional-N all-digital phase-locked loop (ADPLL) suitable for IoT applications. A proposed …
A milliwatt-level 70–110 GHz frequency quadrupler with> 30 dBc harmonic rejection
This article presents a two-channel 70–110-GHz frequency quadrupler in the GF8HP 0.12-
SiGe BiCMOS process. The frequency multiplication is based on cascaded frequency …
SiGe BiCMOS process. The frequency multiplication is based on cascaded frequency …