This paper analyzes the main sources of power consumption in Networks-on-Chip (NoC)-
based systems. Analytical power models of global interconnection links are studied at …

This paper proposes improved structures for fast adders that include carry lookahead (CLA)
and hierarchical carry lookahead (HCLA). Also, it proposes optimized novel structures of …

Abstract Scalable 3D Networks-on-Chip (NoC) designs are needed to match the ever-
increasing communication and low-power demands of large-scale multi-core applications …

Application map** is one of the challenging and most imperative research areas in
Networks on Chip (NoC). Map** of NoC is an NP-hard problem and varieties of heuristics …

Designing power-efficient Networks-on-Chips (NoCs) for 3D ICs has emerged as a
promising solution for complex mobile and portable applications. The total power …

The microthreaded many-core architecture is comprised of multiple clusters of fine-grained
multi-threaded cores. The management of concurrency is supported in the instruction set …

Computer architects are always interested in analyzing the complex interactions amongst
the dynamically allocated resources. Generally a detailed simulator with a cycle-accurate …

This paper introduces performance analysis of 64-bit Carry Lookahead Adders using
conventional and hierarchical structure styles. We evaluate conventional carry lookahead …

Shifting the design entry point up to the system level is the most important countermeasure
adopted to manage the increasing complexity of SoCs. The reason is that decisions taken at …

Network delay is a major design parameter for Networks-on-Chip (NoC)-based applications.
Improving NoC delay could be achieved at different design phases. At the system level, we …