Design and Implementation of a Standard Cell Library for Building Asynchronous ASICS

MT Moreira - Revista da Graduação, 2011 - revistaseletronicas.pucrs.br
Asynchronous ASIC design automation tools and standard cell libraries development lag
behind their synchronous counterpart. Therefore, most asynchronous designs still make use …

FPGA implementation of asynchronous mousetrap pipelined radix-2 CORDIC algorithm

A Changela, M Zaveri, A Lakhlani - … Conference on Current …, 2018 - ieeexplore.ieee.org
The COordinate Rotation DIgital Computer (CORDIC) is a special purpose algorithm to
compute trigonometry functions. CORDIC has achieved attention of many researchers …

Design and implementation of reconfigurable asynchronous pipelines

A de Gennaro, D Sokolov… - IEEE Transactions on Very …, 2020 - ieeexplore.ieee.org
Pipelining is a widely used approach to the design of high-throughput computation systems,
where the slowest component is decomposed into a set of sequentially connected parts that …

A 65 nm gate-level pipelined self-synchronous fpga for high performance and variation robust operation

B Devlin, M Ikeda, K Asada - IEEE journal of solid-state circuits, 2011 - ieeexplore.ieee.org
A 65 nm self-synchronous field programmable gate array (SSFPGA) with delay insensitive
operation and pipeline granularity at the gate level, is shown to be robust to process voltage …

Current sensing methodology for completion detection in self-timed systems

L Nagy, V Stopjaková - 14th IEEE International Symposium on …, 2011 - ieeexplore.ieee.org
This paper addresses an alternative approach in detecting completion of computation in
asynchronous circuits. The proposed method is based on sensing the amount of consumed …

Asynchronous baseband processor design for cooperative MIMO satellite communication

E Rohani, J Xu, T Che, M Rahman… - 2014 IEEE 57th …, 2014 - ieeexplore.ieee.org
The challenges in satellite communication (SatCom) include but not limited to the customary
complications of telecommunication such as channel condition, signal to noise ratio (SNR) …

Five staged pipelined processor with self clocking mechanism

A Gupta, V Kini, P Shetty… - … Conference on Green …, 2015 - ieeexplore.ieee.org
With the advent of synchronous systems we have come across various difficulties and
problems associated with them, mainly like clock skew, power consumption, etc. The idea of …

Accelerated Dual-Path Asynchronous Circuit

T Che, J Xu, G Choi - … Transactions on Circuits and Systems II …, 2015 - ieeexplore.ieee.org
This brief presents a novel design approach that accelerates an asynchronous circuit system
by circumventing transient-fault-induced delays and tolerates latchups and other permanent …

[PDF][PDF] Power-efficient clockless intrachip communication design with an integrated high to low level flow based on the balsa framework

M Moreira, F Magalhães, M Gibiluka, F Hessel… - … Católica do Rio Grande …, 2013 - pucrs.br
The downscaling of silicon technology and the capacity to build entire systems on a chip
have made intrachip communication a relevant research topic. Besides, technology …

Contributions to the Design and Prototy** of GALS and Asynchronous Systems

MT Moreira - 2012 - tede2.pucrs.br
As CMOS technology nodes scale dosn, nes problems a rise concerning the design of
synchronous circuits and systems. This is due to tight constraints resulting from the use of a …