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Survey on chiplets: interface, interconnect and integration methodology
With the end of Moore's Law and Dennard scaling, it has become increasingly difficult to
implement high-performance computing systems on a monolithic chip. The chiplet …
implement high-performance computing systems on a monolithic chip. The chiplet …
[HTML][HTML] The big chip: Challenge, model and architecture
Abstract As Moore's Law comes to an end, the implementation of high-performance chips
through transistor scaling has become increasingly challenging. To improve performance …
through transistor scaling has become increasingly challenging. To improve performance …
A scalable methodology for designing efficient interconnection network of chiplets
The Chiplet methodology can accelerate VLSI system development and provide better
flexibility. However, it is not easy to build interconnection networks across multiple chiplets …
flexibility. However, it is not easy to build interconnection networks across multiple chiplets …
Adapt-noc: A flexible network-on-chip design for heterogeneous manycore architectures
The increased computational capability in heterogeneous manycore architectures facilitates
the concurrent execution of many applications. This requires, among other things, a flexible …
the concurrent execution of many applications. This requires, among other things, a flexible …
A survey of multi-tenant deep learning inference on gpu
Deep Learning (DL) models have achieved superior performance. Meanwhile, computing
hardware like NVIDIA GPUs also demonstrated strong computing scaling trends with 2x …
hardware like NVIDIA GPUs also demonstrated strong computing scaling trends with 2x …
SPACX: Silicon photonics-based scalable chiplet accelerator for DNN inference
In pursuit of higher inference accuracy, deep neural network (DNN) models have
significantly increased in complexity and size. To overcome the consequent computational …
significantly increased in complexity and size. To overcome the consequent computational …
Ascend: A scalable and energy-efficient deep neural network accelerator with photonic interconnects
The complexity and size of recent deep neural network (DNN) models have increased
significantly in pursuit of high inference accuracy. Chiplet-based accelerator is considered a …
significantly in pursuit of high inference accuracy. Chiplet-based accelerator is considered a …
SPRINT: A high-performance, energy-efficient, and scalable chiplet-based accelerator with photonic interconnects for CNN inference
Chiplet-based convolution neural network (CNN) accelerators have emerged as a promising
solution to provide substantial processing power and on-chip memory capacity for CNN …
solution to provide substantial processing power and on-chip memory capacity for CNN …
ReSiPI: A reconfigurable silicon-photonic 2.5 D chiplet network with PCMs for energy-efficient interposer communication
2.5 D chiplet systems have been proposed to improve the low manufacturing yield of large-
scale chips. However, connecting the chiplets through an electronic interposer imposes a …
scale chips. However, connecting the chiplets through an electronic interposer imposes a …
Big-little chiplets for in-memory acceleration of dnns: A scalable heterogeneous architecture
Monolithic in-memory computing (IMC) architectures face significant yield and fabrication
cost challenges as the complexity of DNNs increases. Chiplet-based IMCs that integrate …
cost challenges as the complexity of DNNs increases. Chiplet-based IMCs that integrate …