Survey on chiplets: interface, interconnect and integration methodology

X Ma, Y Wang, Y Wang, X Cai, Y Han - CCF Transactions on High …, 2022 - Springer
With the end of Moore's Law and Dennard scaling, it has become increasingly difficult to
implement high-performance computing systems on a monolithic chip. The chiplet …

[HTML][HTML] The big chip: Challenge, model and architecture

Y Han, H Xu, M Lu, H Wang, J Huang, Y Wang… - Fundamental …, 2024 - Elsevier
Abstract As Moore's Law comes to an end, the implementation of high-performance chips
through transistor scaling has become increasingly challenging. To improve performance …

A scalable methodology for designing efficient interconnection network of chiplets

Y Feng, D **ang, K Ma - 2023 IEEE International Symposium …, 2023 - ieeexplore.ieee.org
The Chiplet methodology can accelerate VLSI system development and provide better
flexibility. However, it is not easy to build interconnection networks across multiple chiplets …

Adapt-noc: A flexible network-on-chip design for heterogeneous manycore architectures

H Zheng, K Wang, A Louri - 2021 IEEE international symposium …, 2021 - ieeexplore.ieee.org
The increased computational capability in heterogeneous manycore architectures facilitates
the concurrent execution of many applications. This requires, among other things, a flexible …

A survey of multi-tenant deep learning inference on gpu

F Yu, D Wang, L Shangguan, M Zhang, C Liu… - arxiv preprint arxiv …, 2022 - arxiv.org
Deep Learning (DL) models have achieved superior performance. Meanwhile, computing
hardware like NVIDIA GPUs also demonstrated strong computing scaling trends with 2x …

SPACX: Silicon photonics-based scalable chiplet accelerator for DNN inference

Y Li, A Louri, A Karanth - 2022 IEEE International Symposium …, 2022 - ieeexplore.ieee.org
In pursuit of higher inference accuracy, deep neural network (DNN) models have
significantly increased in complexity and size. To overcome the consequent computational …

Ascend: A scalable and energy-efficient deep neural network accelerator with photonic interconnects

Y Li, K Wang, H Zheng, A Louri… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
The complexity and size of recent deep neural network (DNN) models have increased
significantly in pursuit of high inference accuracy. Chiplet-based accelerator is considered a …

SPRINT: A high-performance, energy-efficient, and scalable chiplet-based accelerator with photonic interconnects for CNN inference

Y Li, A Louri, A Karanth - IEEE Transactions on Parallel and …, 2021 - ieeexplore.ieee.org
Chiplet-based convolution neural network (CNN) accelerators have emerged as a promising
solution to provide substantial processing power and on-chip memory capacity for CNN …

ReSiPI: A reconfigurable silicon-photonic 2.5 D chiplet network with PCMs for energy-efficient interposer communication

E Taheri, S Pasricha, M Nikdast - Proceedings of the 41st IEEE/ACM …, 2022 - dl.acm.org
2.5 D chiplet systems have been proposed to improve the low manufacturing yield of large-
scale chips. However, connecting the chiplets through an electronic interposer imposes a …

Big-little chiplets for in-memory acceleration of dnns: A scalable heterogeneous architecture

G Krishnan, AA Goksoy, SK Mandal, Z Wang… - Proceedings of the 41st …, 2022 - dl.acm.org
Monolithic in-memory computing (IMC) architectures face significant yield and fabrication
cost challenges as the complexity of DNNs increases. Chiplet-based IMCs that integrate …