Challenges and trends of SRAM-based computing-in-memory for AI edge devices
CJ Jhang, CX Xue, JM Hung… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
When applied to artificial intelligence edge devices, the conventionally von Neumann
computing architecture imposes numerous challenges (eg, improving the energy efficiency) …
computing architecture imposes numerous challenges (eg, improving the energy efficiency) …
Ultra-low power VLSI circuit design demystified and explained: A tutorial
M Alioto - IEEE Transactions on Circuits and Systems I: Regular …, 2012 - ieeexplore.ieee.org
In this paper, the state of the art in ultra-low power (ULP) VLSI design is presented within a
unitary framework for the first time. A few general principles are first introduced to gain an …
unitary framework for the first time. A few general principles are first introduced to gain an …
One-sided schmitt-trigger-based 9T SRAM cell for near-threshold operation
This paper presents a one-sided Schmitt-trigger-based 9T static random access memory cell
with low energy consumption and high read stability, write ability, and hold stability yields in …
with low energy consumption and high read stability, write ability, and hold stability yields in …
A reliable low standby power 10T SRAM cell with expanded static noise margins
E Abbasian, F Izadinasab… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
This paper explores a low standby power 10T (LP10T) SRAM cell with high read stability
and write-ability (RSNM/WSNM/WM). The proposed LP10T SRAM cell uses a strong cross …
and write-ability (RSNM/WSNM/WM). The proposed LP10T SRAM cell uses a strong cross …
Single-ended Schmitt-trigger-based robust low-power SRAM cell
This paper presents a Schmitt-trigger-based single-ended 11T SRAM cell, which
significantly improves read and write static noise margin (SNM) and consumes low power …
significantly improves read and write static noise margin (SNM) and consumes low power …
Ultralow-voltage process-variation-tolerant Schmitt-trigger-based SRAM design
We analyze Schmitt-Trigger (ST)-based differential-sensing static random access memory
(SRAM) bitcells for ultralow-voltage operation. The ST-based SRAM bitcells address the …
(SRAM) bitcells for ultralow-voltage operation. The ST-based SRAM bitcells address the …
40 nm bit-interleaving 12T subthreshold SRAM with data-aware write-assist
YW Chiu, YH Hu, MH Tu, JK Zhao… - … on Circuits and …, 2014 - ieeexplore.ieee.org
This paper presents a new bit-interleaving 12T subthreshold SRAM cell with Data-Aware
Power-Cutoff (DAPC) Write-assist to improve the Write-ability to mitigate increased device …
Power-Cutoff (DAPC) Write-assist to improve the Write-ability to mitigate increased device …
A single-ended disturb-free 9T subthreshold SRAM with cross-point data-aware write word-line structure, negative bit-line, and adaptive read operation timing tracing
MH Tu, JY Lin, MC Tsai, CY Lu, YJ Lin… - IEEE Journal of Solid …, 2012 - ieeexplore.ieee.org
This paper presents a novel single-ended disturb-free 9T subthreshold SRAM cell with cross-
point data-aware Write word-line structure. The disturb-free feature facilitates bit-interleaving …
point data-aware Write word-line structure. The disturb-free feature facilitates bit-interleaving …
Variation tolerant differential 8T SRAM cell for ultralow power applications
Low power and noise tolerant static random access memory (SRAM) cells are in high
demand today. This paper presents a stable differential SRAM cell that consumes low …
demand today. This paper presents a stable differential SRAM cell that consumes low …
A 62 mV 0.13 m CMOS Standard-Cell-Based Design Technique Using Schmitt-Trigger Logic
N Lotze, Y Manoli - IEEE journal of solid-state circuits, 2011 - ieeexplore.ieee.org
Supply voltage reduction beyond the minimum energy per operation point is advantageous
for supply voltage constrained applications, but is limited by the degradation of on-to-off …
for supply voltage constrained applications, but is limited by the degradation of on-to-off …