Reconfiguration technique for reducing test time and test data volume in Illinois scan architecture based designs

AR Pandey, JH Patel - … 20th IEEE VLSI Test Symposium (VTS …, 2002 - ieeexplore.ieee.org
As the complexity of VLSI circuits is increasing due to the exponential rise in transistor count
per chip, testing cost is becoming an important factor in the overall integrated circuit (IC) …

Impact of process-variations in STTRAM and adaptive boosting for robustness

S Motaman, S Ghosh, N Rathi - … & Test in Europe Conference & …, 2015 - ieeexplore.ieee.org
Spin-Torque Transfer Random Access Memory (STTRAM) is a promising technology for
high density on-chip cache due to low standby power. Additionally, it offers fast access time …

A survey and perspective on artificial intelligence for security-aware electronic design automation

D Koblah, R Acharya, D Capecci… - ACM Transactions on …, 2023 - dl.acm.org
Artificial intelligence (AI) and machine learning (ML) techniques have been increasingly
used in several fields to improve performance and the level of automation. In recent years …

Nenofex: Expanding NNF for QBF solving

F Lonsing, A Biere - International Conference on Theory and Applications …, 2008 - Springer
The topic of this paper is Nenofex, a solver for quantified boolean formulae (QBF) in
negation normal form (NNF), which relies on expansion as the core technique for eliminating …

On the cost-effectiveness of matching repositories of pre-tested wafers for wafer-to-wafer 3D chip stacking

J Verbree, EJ Marinissen, P Roussel… - 2010 15th IEEE …, 2010 - ieeexplore.ieee.org
Three-dimensional stacked ICs (3D-SICs) based on Through-Silicon Vias (TSV) promise
high-performance low-power functionality in a smaller form factor at lower cost. Stacking …

Enhancement of the Illinois scan architecture for use with multiple scan inputs

MA Shah, JH Patel - IEEE Computer Society Annual …, 2004 - ieeexplore.ieee.org
Testing cost is becoming increasingly important as system-on-chip circuits continue to
become more complex. In this paper, we address the issue of reducing test cost by …

BIST architecture for multiple RAMs in SoC

PK John - Procedia computer science, 2017 - Elsevier
Testing of Memory cores has an important role in the process of testing System-on-Chip
(SoC) for detecting faults and improving overall yield and quality. Most common method …

CircularScan: a scan architecture for test cost reduction

B Arslan, A Orailoglu - … Design, Automation and Test in Europe …, 2004 - ieeexplore.ieee.org
Scan-based designs are widely used to decrease the complexity of the test generation
process; nonetheless, they increase test time and volume. A new scan architecture is …

An open-source verification framework for open-source cores: A RISC-V case study

PD Schiavone, E Sanchez, A Ruospo… - 2018 IFIP/IEEE …, 2018 - ieeexplore.ieee.org
The complexity and heterogeneity of digital devices used in embedded systems is
increasing everyday and delivering a bug-free design is still a very complex task. The …

An incremental algorithm for test generation in Illinois scan architecture based designs

AR Pandey, JH Patel - … 2002 Design, Automation and Test in …, 2002 - ieeexplore.ieee.org
As the complexity of VLSI circuits is increasing due to the exponential rise in transistor count
per chip, testing cost is becoming an important factor in the overall integrated circuit (IC) …