Bridging high-level synthesis and application-specific arithmetic: The case study of floating-point summations
FPGAs are well known for their ability to perform non-standard computations not supported
by classical microprocessors. Many libraries of highly customizable application-specific IPs …
by classical microprocessors. Many libraries of highly customizable application-specific IPs …
Application-specific arithmetic in high-level synthesis tools
This work studies hardware-specific optimization opportunities currently unexploited by high-
level synthesis compilers. Some of these optimizations are specializations of floating-point …
level synthesis compilers. Some of these optimizations are specializations of floating-point …
Architectural Synthesis of Fixed‐Point DSP Datapaths Using FPGAs
G Caffarena, JA López, G Leyva… - International Journal …, 2009 - Wiley Online Library
We address the automatic synthesis of DSP algorithms using FPGAs. Optimized fixed‐point
implementations are obtained by means of considering (i) a multiple wordlength …
implementations are obtained by means of considering (i) a multiple wordlength …
Simulated annealing‐based high‐level synthesis methodology for reliable and energy‐aware application specific integrated circuit designs with multiple supply …
Integrated circuits have become more vulnerable to soft errors due to smaller transistor sizes
and lower threshold voltage levels. Energy reduction methods make circuits more error …
and lower threshold voltage levels. Energy reduction methods make circuits more error …
Architectural synthesis of DSP circuits under simultaneous error and time constraints
G Caffarena, C Carreras - … Conference on VLSI and System-on …, 2010 - ieeexplore.ieee.org
In this paper, the design tasks of wordlength optimization and architectural synthesis are
combined. The benefits in comparison to the traditional sequential application of these two …
combined. The benefits in comparison to the traditional sequential application of these two …
High-level synthesis and arithmetic optimizations
Y Uguen - 2019 - hal.science
High-level synthesis (HLS) tools offer increased productivity regarding FPGA programming.
However, due to their relatively young nature, they still lack many arithmetic optimizations …
However, due to their relatively young nature, they still lack many arithmetic optimizations …
A fast interpolative wordlength optimization method for dsp systems
As Digital Signal Processing (DSP) systems grow in complexity, the classical simulation-
based approaches to the wordlength optimization (WLO) problem for fixed-point data …
based approaches to the wordlength optimization (WLO) problem for fixed-point data …
Optimized architectural synthesis of fixed-point datapaths
In this paper we address the time-constrained architectural synthesis of fixed-point DSP
algorithms using FPGA devices. Optimized fixed-point implementations are obtained by …
algorithms using FPGA devices. Optimized fixed-point implementations are obtained by …
A Three-Axis Finger Force Sensor Using Single-layer and Disc-Shaped Sensitive Plate
M Zhu - 2010 International Conference on Measuring …, 2010 - ieeexplore.ieee.org
In this paper, a three-axis finger force sensor with force-sensing part in the form of a thin disc-
shaped alloy plate is presented. Different from the traditional and bulky sensitive element …
shaped alloy plate is presented. Different from the traditional and bulky sensitive element …
A high-level synthesis approach optimizing accumulations in floating-point programs using custom formats and operators
High-level synthesis (HLS) is a big step forward in terms of design productivity. However, it
restricts data-types and operators to those available in the C language supported by the …
restricts data-types and operators to those available in the C language supported by the …