An overview of through-silicon-via technology and manufacturing challenges

JP Gambino, SA Adderly, JU Knickerbocker - Microelectronic Engineering, 2015 - Elsevier
The idea of using through-silicon-via (TSV) technology has been around for many years.
However, this technology has only recently been introduced into high volume …

A review of recent research on heat transfer in three-dimensional integrated circuits (3-D ICs)

SS Salvi, A Jain - IEEE Transactions on Components …, 2021 - ieeexplore.ieee.org
Three-dimensional integrated circuits (3-D IC) technology has emerged in the past few
decades, driven in part by the techno-economic difficulties of dimensional scaling and the …

A survey of optimization techniques for thermal-aware 3D processors

K Cao, J Zhou, T Wei, M Chen, S Hu, K Li - Journal of Systems Architecture, 2019 - Elsevier
Interconnect scaling has become a major design challenge for traditional planar (2D)
integrated circuits (ICs). Three-dimensional (3D) IC that stacks multiple device layers …

TSV-based 3-D ICs: Design methods and tools

T Lu, C Serafy, Z Yang, SK Samal… - … on Computer-Aided …, 2017 - ieeexplore.ieee.org
Vertically integrated circuits (3-D ICs) may revitalize Moore's law scaling which has slowed
down in recent years. 3-D stacking is an emerging technology that stacks multiple dies …

Thermal design and constraints for heterogeneous integrated chip stacks and isolation technology using air gap and thermal bridge

Y Zhang, Y Zhang, MS Bakir - IEEE Transactions on …, 2014 - ieeexplore.ieee.org
This paper summarizes the thermal challenges in conventional 3-D stacks and proposes a
novel stacking structure that eases the thermal problem. The objective of this paper is first to …

Adaptive regression-based thermal modeling and optimization for monolithic 3-D ICs

SK Samal, S Panth, K Samadi, M Saeidi… - … on Computer-Aided …, 2016 - ieeexplore.ieee.org
In this paper, we first present a comprehensive study of the unique thermal behavior in
monolithic 3-D integrated circuits (ICs) in contrast to through silicon via-based 3-D ICs. In …

Benchmarking digital die-to-die channels in 2.5-D and 3-D heterogeneous integration platforms

Y Zhang, X Zhang, MS Bakir - IEEE Transactions on Electron …, 2018 - ieeexplore.ieee.org
In this paper, compact circuit models and HSPICE simulations are used to benchmark die-to-
die communication channels in 2.5-D and 3-D heterogeneous integration platforms. The …

Stacking signal TSV for thermal dissipation in global routing for 3-D IC

PY Hsu, HT Chen, TT Hwang - IEEE Transactions on Computer …, 2014 - ieeexplore.ieee.org
With no further shrinking of device size, 3-D chip stacking by through-silicon-via (TSV) has
been identified as an effective way to achieve better performance in speed and power …

Machine learning based effective linear regression model for TSV layer assignment in 3DIC

K Pandiaraj, P Sivakumar, KJ Prakash - Microprocessors and …, 2021 - Elsevier
On the integration of 3D IC design, thermal management issues play a significant role. So, it
is required to implement an effective approaches and solutions for integrating 3DIC. The …

Design automation and test solutions for monolithic 3D ICs

L Zhu, A Chaudhuri, S Banerjee, G Murali… - ACM Journal on …, 2021 - dl.acm.org
Monolithic 3D (M3D) is an emerging heterogeneous integration technology that overcomes
the limitations of the conventional through-silicon-via (TSV) and provides significant …