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A 0.3 V 8-bit 8.9 fJ/con.-step SAR ADC with sub-DAC merged switching for bio-sensors
W Guo, Z Zhu - Microelectronics journal, 2017 - Elsevier
Abstract An 8-bit 10 kS/s 0.3 V ultra-low power successive approximation register (SAR)
analog-to-digital converter (ADC) is proposed. On account of the presented sub-DAC …
analog-to-digital converter (ADC) is proposed. On account of the presented sub-DAC …
A low power dynamic comparator for a 12-bit pipelined successive approximation register (SAR) ADC
DS Shylu, S Jasmine, DJ Moni - 2018 4th International …, 2018 - ieeexplore.ieee.org
210MS/s 12-bit pipelined SAR ADC that can be used for mobile applications consists of
various components that can reduce the precision and the power consumption of the device …
various components that can reduce the precision and the power consumption of the device …
A testbed for adaptive microphones in ultra-low-power systems
Smart cities bring new technological advances that help improve everyday life. One such
improvement is the ability to map out a city based on a characteristic. The amount of acoustic …
improvement is the ability to map out a city based on a characteristic. The amount of acoustic …
[HTML][HTML] A digital interface asic for triple-axis mems vibratory gyroscopes
R Lv, Q Fu, W Chen, L Yin, X Liu, Y Zhang - Sensors, 2020 - mdpi.com
This paper proposes a solution for sensing spatial angular velocity. A high-performance
digital interface application specific integrated circuit (ASIC) for triple-axis micro …
digital interface application specific integrated circuit (ASIC) for triple-axis micro …
Signal recovery performance analysis in wireless sensing with rectangular-type analog joint source-channel coding
The signal recovery performance of the rectangular-type Analog Joint Source-Channel
Coding (AJSCC) is analyzed in this work for high and medium/low Signal-to-Noise Ratio …
Coding (AJSCC) is analyzed in this work for high and medium/low Signal-to-Noise Ratio …
An efficient-energy switching scheme with 99.57% reduction in switching energy for SAR ADC
R Ding, C Tan, Y Li, S Liu, Z Zhu - Analog Integrated Circuits and Signal …, 2019 - Springer
An efficient-energy switching scheme for a successive approximation register (SAR)
analogue-to-digital converter (ADC) is presented. The proposed switching scheme …
analogue-to-digital converter (ADC) is presented. The proposed switching scheme …
13 位高无杂散动态范围的 SAR ADC
杨志新， 高博， 龚敏 - 电子与封装, 2022 - ep.org.cn
基于标准0.18 μm CMOS 工艺, 设计了一款采样率为500 kS/s 的13 位逐次逼**型模数转换器(
Successive Approximation Analog-to-Digital Converter, SAR ADC) 芯片 …
Successive Approximation Analog-to-Digital Converter, SAR ADC) 芯片 …
The Design of two Low Power 10-bit/12-Bit 100-KS/s Hybrid/Split-Capacitor SAR ADCs and an Electrode-Tissue Impedance Measurement Circuit for Implantable …
CH Chung - 2019 - search.proquest.com
Two SAR ADCs and an electrode-tissue impedance measurement circuit are designed for
implantable medical device, such as epileptic seizure control SoC. To minimize the power …
implantable medical device, such as epileptic seizure control SoC. To minimize the power …
Statistical Estimator Aided SAR ADC Design for Noise and Mismatch Suppression
A Ganesh - 2018 - search.proquest.com
In this thesis, a statistical estimator based successive approximation register (SAR) analog
to digital converter (ADC) is designed. This statistical estimator works based on maximum …
to digital converter (ADC) is designed. This statistical estimator works based on maximum …
130nm CMOS SAR-ADC with Low Complexity Digital Control Logic
M Borgarino, N Verrascina, JB Begueret - Sensors & Transducers, 2018 - iris.unimore.it
This paper reports on an original approach to design the digital control logic of a Successive
Approximation Register Analog to Digital Converter, where no sequencers or code registers …
Approximation Register Analog to Digital Converter, where no sequencers or code registers …