Networks-on-Chip constitute the interconnection architecture of future, massively parallel
multiprocessors that assemble hundreds to thousands of processing cores on a single chip …

To alleviate the complex communication problems that arise as the number of on-chip
components increases, network-on-chip (NoC) architectures have been recently proposed …

A path profile determines how many times each acyclic path in a routine executes. This type
of profiling subsumes the more common basic block and edge profiling, which only …

The advent of deep sub-micron technology has exacerbated reliability issues in on-chip
interconnects. In particular, single event upsets, such as soft errors, and hard faults are …

Billion transistor systems-on-chip increasingly require dynamic management of their
hardware components and careful coordination of the tasks that they carry out. Diverse real …

This paper gives an overview of state-of-the-art regarding the network-on-chip (NoC)
proposals. NoC paradigm replaces dedicated, design-specific wires with scalable, general …

Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip:
The Next Generation of System-on-Chip Integration examines the current issues restricting …

We propose an analytical model based on queueing theory for delay analysis in a wormhole-
switched network-on-chip (NoC). The proposed model takes as input an application …

This book discusses new techniques for detecting, controlling, and exploiting the impacts of
temperature variations on nanoscale circuits and systems. A new sensor system is …

Continuing decrease in the feature size of integrated circuits leads to increases in
susceptibility to transient and permanent faults. This paper proposes a fault-tolerant solution …