The primary focus of this paper is to discuss the modeling of jitter caused by power supply
noise (PSN), named power supply induced jitter (PSIJ). A holistic discussion is presented …

In this article, a knowledge-based artificial neural network (ANN) is developed for predicting
jitter in CMOS inverter circuits in the presence of power supply noise (PSN). The proposed …

This article proposes a jitter-aware decoupling capacitors placement optimization method
that uses the genetic algorithm (GA). A novel method for defining the optimization target …

This paper presents an efficient method to estimate jitter in a chain of CMOS inverters in the
presence of multiple noise sources, including the power supply noise, input data noise, and …

Precise analytical models of power supply noise induced jitter (PSIJ) at inverter chains are
proposed. Based on the piecewise linear approximated IV curve model, analytical models of …

This article presents an analytical approach to determine jitter for a CMOS inverter in the
presence of power supply noise (PSN). The deviation in the transition edge of the output …

With the advancement of semiconductor technology (enabling the dimensions of the
switching devices in the range of nanometer scale) designing, modeling, and optimization of …

Heterogeneous integration allows multiple silicon dies of various technologies and
complexity to communicate efficiently using second-level interconnects, interposers, in a …

An efficient method is presented for estimation of power supply induced jitter (PSIJ). The
proposed method is based on advancing the recently proposed EMPSIJ method and …

In this paper, we first propose a methodology to predict Power Supply Noise Induced Jitter
(PSIJ) by accurately measuring Jitter Sensitivity Function (JSF) and Power Supply Noise …