HW/SW co-design toolset for customization of exposed datapath processors
Customized processors are an interesting option for implementing software defined radios;
they bring benefits of tailored fixed function hardware while adding new advantages such as …
they bring benefits of tailored fixed function hardware while adding new advantages such as …
Allocation and scheduling of dataflow graphs on hybrid dataflow/von Neumann architectures
A Bhagyanath, N Kercher, K Schneider - Proceedings of the 21st ACM …, 2023 - dl.acm.org
Hybrid dataflow/von Neumann processors expose their processing units and datapaths to
the compiler to exploit the instruction-level parallelism of sequential programs. Generating …
the compiler to exploit the instruction-level parallelism of sequential programs. Generating …
A 4W Low-Power Audio Processor System for Real-Time Jaw Movements Recognition in Grazing Cattle
LS Martinez-Rau, M Weißbrich… - Journal of Signal …, 2023 - Springer
Precision livestock farming consists of technological tools and techniques to improve
livestock management. Proper detection and classification of jaw movement (JM) events are …
livestock management. Proper detection and classification of jaw movement (JM) events are …
Performance analysis of selected programming languages in the context of supporting decision-making processes for industry 4.0
This study analyzes the possibility of using Go (Golang) in the context of Java and Python in
decision-making processes, with particular emphasis on their use in industry-specific …
decision-making processes, with particular emphasis on their use in industry-specific …
Transport-triggered soft cores
Soft cores are used as flexible software programmable components in FPGA designs.
Transport-Triggered Architecture (TTA) is interesting for this use due to its scalability …
Transport-Triggered Architecture (TTA) is interesting for this use due to its scalability …
Ballast: Implementation of a large MP-SoC on 22nm ASIC technology
Chips have become the critical asset of the technology, and increasing effort is put to design
System-on-Chips (SoC) faster and more affordable. Typically the focus of the research has …
System-on-Chips (SoC) faster and more affordable. Typically the focus of the research has …
Energy-Efficient Exposed Datapath Architecture With a RISC-V Instruction Set Mode
Transport triggered architectures (TTAs) follow the static programming model of very long
instruction word (VLIW) processors but expose additional information of the processor …
instruction word (VLIW) processors but expose additional information of the processor …
Towards buffers as a scalable alternative to registers for processor-local memory
J Roob, A Bhagyanath… - MBMV 2023; 26th …, 2023 - ieeexplore.ieee.org
Processors require local memory close to the execution units to bridge the long latencies for
accessing the comparatively slow main memory. In particular, traditional processor …
accessing the comparatively slow main memory. In particular, traditional processor …
OpenASIP 2.0: co-design toolset for RISC-V application-specific instruction-set processors
Application-specific instruction-set processors (ASIPs) are interesting for improving
performance or energy-efficiency for a set of applications of interest while supporting …
performance or energy-efficiency for a set of applications of interest while supporting …
Program balancing in compilation for buffered hybrid dataflow processors
A Bhagyanath, K Schneider - 2023 IEEE 47th Annual …, 2023 - ieeexplore.ieee.org
In traditional von Neumann processors, the central register file is an inherent limiting factor
in exploiting the instruction-level parallelism (ILP) of programs. To alleviate this problem …
in exploiting the instruction-level parallelism (ILP) of programs. To alleviate this problem …