This book presents an overview of the issues related to the test, diagnosis and fault-
tolerance of Network on Chip-based systems. It is the first book dedicated to the quality …

This paper proposes a built-in self-test/self-diagnosis procedure at start-up of an on-chip
network (NoC). Concurrent BIST operations are carried out after reset at each switch, thus …

This paper describes a new approach towards dependable design of homogeneous multi-
processor SoCs in an example satellite-navigation application. First, the NoC dependability …

As complexity and size of Systems-on-Chip (SoC) grow, debugging becomes a bottleneck
for designing IC products. In this paper, we present an approach for online debug of NoC …

Software-Based Self-Test (SBST) is extended to the switches of complex Network-on-Chips
(NoC). Test patterns for structural faults are turned into valid packets by using satisfiability …

The focus of the paper is detection of faults in NoC routers by combining concurrent
checkers with embedded on-line test to enable cost-effective trade-offs between area …

Networks-on-Chip (NoCs) are implicitly fault tolerant due to their inherent redundancy. They
can overcome defective cores, links and switches. As a side effect, yield is increased at the …

Different approaches have been proposed for automating pre-silicon and post-silicon
debugging. Automated approaches in pre-silicon debugging rely on simulation [VH99], BDD …

Reconfigurable Networks-on-Chip (NoCs) allow discarding the corrupted ports of a defective
switch instead of deactivating it entirely, and thus enable fine-grained reconfiguration of the …

Abstract On-Chip Networks (OCN s) have been proposed to solve the complex on-chip
communication problems. In Very Deep-Submicron era, OCN will also be affected by faults …