The traditional purpose of physical synthesis is to perform timing closure, ie, to create a
placed design that meets its timing specifications while also satisfying electrical, routability …

This paper presents Yasper, a tool for modeling, analyzing and simulating workflow systems,
based on Petri nets. Yasper puts Petri net modeling in the hands of business analysts and …

Closed-form expressions for buffered interconnect delay approximation have been around
for some time. However, previous approaches assume that buffers are free to be placed …

This chapter addresses several variations of the corresponding fundamental Steiner minimal
tree problem, where a given set of pins is to be connected using minimum total wirelength. It …

In interconnect bus coding techniques the presence of buffers is often ignored. Buffers are
used to restore the signal level affected by parasitics. However buffers have a certain …

The clock trees of high-performance synchronous circuits have many clock logic cells (eg,
clock gating cells, multiplexers and dividers) in order to achieve aggressive clock gating and …

Buffer insertion and wire sizing are critical in deep submicron VLSI design. This paper
studies the problem of constructing routing trees with simultaneous buffer insertion and wire …

In VLSI interconnects, buffers are used to restore the signal level affected by the parasitic
such as line capacitance, inductance, etc.. However buffers have a certain switching time …

This paper studies the impacts of Chemical Mechanical Polishing (CMP)-induced systematic
variation and random channel length (L eff) variation of transistors on interconnect design …

Buffer insertion is a fundamental technology for VLSI interconnect optimization. Several
existing buffer insertion algorithms have evolved from van Ginneken's classic algorithm. In …