A Network Coding Based Functional Test Method for the Routers in 3D Mesh NoCs
C Wei, X Cui - IEEE Internet of Things Journal, 2024 - ieeexplore.ieee.org
The three-dimensional (3D) Mesh network-on-chip (NoC) is widely used as the
communication backbone of the 3D multi-processor system-on-chips (MPSoCs) and chiplet …
communication backbone of the 3D multi-processor system-on-chips (MPSoCs) and chiplet …
TSV BIST Repair: Design-For-Test Challenges and Emerging Solution for 3D Stacked IC's
A Sankararao, G Vaishnavi… - 2022 IEEE International …, 2022 - ieeexplore.ieee.org
The efficient methodology to increase the yield and performance of 3D Stacked Integrated-
Circuits (3D SICs) using TSV BIST Repair mechanism is addressed in this paper. This …
Circuits (3D SICs) using TSV BIST Repair mechanism is addressed in this paper. This …
A Single-TSV and Single-DCDL Approach for Skew Compensation of Multi-Dies Clock Synchronization in 3-D-ICs
Existing methods used for the clock distribution of multiple dies employ a balanced tree
structure to minimize the impact of the within-die process and loading variations. No …
structure to minimize the impact of the within-die process and loading variations. No …
Selective fault-masking for improving yield and performance of on-chip networks
Nowadays, the reliability in network-on-chip (NoC) has become a crucial issue that leads to
network performance degradation. Built-in-self-test (BIST) is one of the primary test schemes …
network performance degradation. Built-in-self-test (BIST) is one of the primary test schemes …
[PDF][PDF] 適応型デジタルニューロモーフィックシステムの設計について
オグボドマーク イケチュク - u-aizu.repo.nii.ac.jp
Traditional computer systems have significantly advanced over the years, demonstrating
tremendous performance in high precision numerical computations. They are based on the …
tremendous performance in high precision numerical computations. They are based on the …