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A survey on two-dimensional Error Correction Codes applied to fault-tolerant systems
The number of memory faults operating in radiation environments increases with the
electronic device miniaturization. One-dimensional (1D) Error Correction Codes (ECCs) are …
electronic device miniaturization. One-dimensional (1D) Error Correction Codes (ECCs) are …
Low cost and highly reliable radiation hardened latch design in 65 nm CMOS technology
C Qi, L **ao, J Guo, T Wang - Microelectronics reliability, 2015 - Elsevier
As a consequence of technology scaling down, gate capacitances and stored charge in
sensitive nodes are decreasing rapidly, which makes CMOS circuits more vulnerable to …
sensitive nodes are decreasing rapidly, which makes CMOS circuits more vulnerable to …
Enhanced memory reliability against multiple cell upsets using decimal matrix code
Transient multiple cell upsets (MCUs) are becoming major issues in the reliability of
memories exposed to radiation environment. To prevent MCUs from causing data …
memories exposed to radiation environment. To prevent MCUs from causing data …
ECC-united cache: Maximizing efficiency of error detection/correction codes in associative cache memories
Error Detection/Correction Codes (EDCs/ECCs) are the most conventional approaches to
protect on-chip caches against radiation-induced soft errors. The overhead of EDCs/ECCs is …
protect on-chip caches against radiation-induced soft errors. The overhead of EDCs/ECCs is …
A correction code for multiple cells upsets in memory devices for space applications
As the microelectronics technology continuously scales down, the probability of multiple cell
upsets (MCUs) induced by radiation in memory devices increases. It is required a robust …
upsets (MCUs) induced by radiation in memory devices increases. It is required a robust …
SEU tolerant memory using error correction code
X She, N Li, DW Jensen - IEEE Transactions on Nuclear …, 2012 - ieeexplore.ieee.org
With decreasing circuit lithography dimensions and increasing memory densities, an SEU
may affect multiple adjacent memory cells. This paper presents an SEU hardened memory …
may affect multiple adjacent memory cells. This paper presents an SEU hardened memory …
Low redundancy matrix-based codes for adjacent error correction with parity sharing
As CMOS technology scales down, multiple cell upsets (MCUs) caused by a single radiation
particle have become one of the most challenging reliability issues for memories in space …
particle have become one of the most challenging reliability issues for memories in space …
Compact and power efficient SEC-DED codec for computer memory
Frequently, soft errors occur due to striking of radioactive particles in memory cells which
reduce the reliability of memory systems. Generally, single error correction-double error …
reduce the reliability of memory systems. Generally, single error correction-double error …
Raw-tag: replicating in altered cache ways for correcting multiple-bit errors in tag array
Tag array in on-chip caches is one of the most vulnerable components to radiation-induced
soft errors. Protecting the tag array in some processors is limited to error detection using the …
soft errors. Protecting the tag array in some processors is limited to error detection using the …
SEU hardened flip-flop based on dynamic logic
SX Xuan, N Li, J Tong - IEEE Transactions on Nuclear Science, 2013 - ieeexplore.ieee.org
A conventional master-slave flip-flop is very sensitive to particle strike that causes an SEU.
When the clock is high, an SEU may upset the logic state of the master latch resulting in a …
When the clock is high, an SEU may upset the logic state of the master latch resulting in a …