Applying partial reconfiguration to networks-on-chips
T Pionteck, R Koch, C Albrecht - 2006 International Conference …, 2006 - ieeexplore.ieee.org
This paper presents CoNoChi, an adaptable network-on-chip for dynamically reconfigurable
hardware designs. CoNoChi is designed for taking advantage of the partial dynamic …
hardware designs. CoNoChi is designed for taking advantage of the partial dynamic …
[PDF][PDF] An evaluation of dynamic partial reconfiguration for signal and image processing in professional electronics applications
P Manet, D Maufroid, L Tosi, G Gailliard… - EURASIP Journal on …, 2009 - Springer
Signal and image processing applications require a lot of computing resources. For low-
volume applications like in professional electronics applications, FPGA are used in …
volume applications like in professional electronics applications, FPGA are used in …
Reconfigurable networks on chip: DRNoC architecture
To cover the complexity of future systems, where thousands and hundreds of heterogeneous
cores have to be interconnected, new on-chip communication solutions are being searched …
cores have to be interconnected, new on-chip communication solutions are being searched …
A reconfigurable computing platform for real time embedded applications
Reconfigurable computing is a promising technique for real time computing-intensive
embedded applications. In this paper, we propose a novel hardware task model and an …
embedded applications. In this paper, we propose a novel hardware task model and an …
Learning-based adaptation to applications and environments in a reconfigurable network-on-chip
The set of applications communicating via a Network-on-Chip (NoC) and the NoC itself both
have varying run-time requirements on reliability and power-efficiency. To meet these …
have varying run-time requirements on reliability and power-efficiency. To meet these …
A multi–level design methodology of multistage interconnection network for MPSOCs
In this paper, we propose a design methodology of Multistage Interconnection Networks
(MINs) for multiprocessor system on chip. The framework covers the design step from …
(MINs) for multiprocessor system on chip. The framework covers the design step from …
Run-time reconfigurable network-on-chip: A survey
Network-on-chip (NoC) is a promising communication medium for multi-processor SoCs.
However, the increasing demand of flexible use-cases in SoC applications triggers …
However, the increasing demand of flexible use-cases in SoC applications triggers …
ReNo: novel switch architecture for reliability improvement of NoCs
Using of nano-scale Very Large-Scale Integration technologies in Network-on-Chips
(NoCs), switches and communication wires of NoCs are sensitive to transient faults. In the …
(NoCs), switches and communication wires of NoCs are sensitive to transient faults. In the …
Design of a reconfigurable network-on-chip for next generation FPGAs using Dynamic Partial Reconfiguration
R Ahmed, H Mostafa, AH Khalil - Microelectronics Journal, 2021 - Elsevier
Introducing the reconfigurability concept into one of the most ram** and trending design
platforms like the NoC is considered a good opportunity for gaining the most out of them …
platforms like the NoC is considered a good opportunity for gaining the most out of them …
Dynamically reconfigurable architectures for software-defined radio in professional electronic applications
B Rousseau, P Manet, T Delavallée, I Loiselle… - Design technology for …, 2012 - Springer
Professional embedded electronic applications are found in military, security, or high
reliability systems like in avionics and aerospace. They have to meet specific requirements …
reliability systems like in avionics and aerospace. They have to meet specific requirements …