Applying partial reconfiguration to networks-on-chips

T Pionteck, R Koch, C Albrecht - 2006 International Conference …, 2006 - ieeexplore.ieee.org
This paper presents CoNoChi, an adaptable network-on-chip for dynamically reconfigurable
hardware designs. CoNoChi is designed for taking advantage of the partial dynamic …

[PDF][PDF] An evaluation of dynamic partial reconfiguration for signal and image processing in professional electronics applications

P Manet, D Maufroid, L Tosi, G Gailliard… - EURASIP Journal on …, 2009 - Springer
Signal and image processing applications require a lot of computing resources. For low-
volume applications like in professional electronics applications, FPGA are used in …

Reconfigurable networks on chip: DRNoC architecture

YE Krasteva, E De la Torre, T Riesgo - Journal of Systems Architecture, 2010 - Elsevier
To cover the complexity of future systems, where thousands and hundreds of heterogeneous
cores have to be interconnected, new on-chip communication solutions are being searched …

A reconfigurable computing platform for real time embedded applications

F Say, CF Bazlamaçcı - Microprocessors and Microsystems, 2012 - Elsevier
Reconfigurable computing is a promising technique for real time computing-intensive
embedded applications. In this paper, we propose a novel hardware task model and an …

Learning-based adaptation to applications and environments in a reconfigurable network-on-chip

JS Shen, CH Huang, PA Hsiung - 2010 Design, Automation & …, 2010 - ieeexplore.ieee.org
The set of applications communicating via a Network-on-Chip (NoC) and the NoC itself both
have varying run-time requirements on reliability and power-efficiency. To meet these …

A multi–level design methodology of multistage interconnection network for MPSOCs

Y Aydi, M Baklouti, M Abid… - International journal of …, 2011 - inderscienceonline.com
In this paper, we propose a design methodology of Multistage Interconnection Networks
(MINs) for multiprocessor system on chip. The framework covers the design step from …

Run-time reconfigurable network-on-chip: A survey

HL Kidane, EB Bourennane - 2018 15th International Multi …, 2018 - ieeexplore.ieee.org
Network-on-chip (NoC) is a promising communication medium for multi-processor SoCs.
However, the increasing demand of flexible use-cases in SoC applications triggers …

ReNo: novel switch architecture for reliability improvement of NoCs

Z Shirmohammadi, Y Allivand, F Mozafari… - The Journal of …, 2023 - Springer
Using of nano-scale Very Large-Scale Integration technologies in Network-on-Chips
(NoCs), switches and communication wires of NoCs are sensitive to transient faults. In the …

Design of a reconfigurable network-on-chip for next generation FPGAs using Dynamic Partial Reconfiguration

R Ahmed, H Mostafa, AH Khalil - Microelectronics Journal, 2021 - Elsevier
Introducing the reconfigurability concept into one of the most ram** and trending design
platforms like the NoC is considered a good opportunity for gaining the most out of them …

Dynamically reconfigurable architectures for software-defined radio in professional electronic applications

B Rousseau, P Manet, T Delavallée, I Loiselle… - Design technology for …, 2012 - Springer
Professional embedded electronic applications are found in military, security, or high
reliability systems like in avionics and aerospace. They have to meet specific requirements …