New structure transistors for advanced technology node CMOS ICs

Q Zhang, Y Zhang, Y Luo, H Yin - National Science Review, 2024 - academic.oup.com
Over recent decades, advancements in complementary metal-oxide-semiconductor
integrated circuits (ICs) have mainly relied on structural innovations in transistors. From …

Spacer engineering on multi-channel FinFET for advanced wireless applications

VB Sreenivasulu, S Bhandari, M Prasad, P Mani… - … -International Journal of …, 2024 - Elsevier
Wireless applications require a low power technology that enables DC/analog/RF functions
on the same chip. It is well established fact that Multi-channel FinFET (Multifin) enhances the …

Vertically stacked gate-all-around Si nanowire CMOS transistors with reduced vertical nanowires separation, new work function metal gate solutions, and DC/AC …

R Ritzenthaler, H Mertens, V Pena… - 2018 IEEE …, 2018 - ieeexplore.ieee.org
We report on vertically stacked gate-all-around (GAA) Si nanowire (NW) MOSFETs,
integrated in a CMOS dual Work Function Metal Replacement Metal Gate (RMG) flow. The …

Design insights into RF/analog and linearity/distortion of spacer engineered multi‐fin SOI FET for terahertz applications

VB Sreenivasulu, V Narendar - International Journal of RF and …, 2021 - Wiley Online Library
Multi‐fin devices are the most reliable option for terahertz (THz) frequency applications at
nano‐regime. In this work impact of spacer engineering on multi‐fin SOI FET performance is …

Comparison of electrical performance of co-integrated forksheets and nanosheets transistors for the 2nm technological node and beyond

R Ritzenthaler, H Mertens, G Eneman… - 2021 IEEE …, 2021 - ieeexplore.ieee.org
Forksheet devices have been recently proposed to further reduce the n-to-p
spacing/footprint of transistors on wafer. In this work, we report on a systematic comparison …

The impact of fin number on device performance and reliability for multi-fin tri-gate n-and p-type FinFET

WK Yeh, W Zhang, PY Chen… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
In this paper, the effect of carrier quantization on device characteristics and stress-induced
device degradation for multifin high-κ/metal tri-gate n-type and p-type fin field-effect …

Reduction of process variations for sub-5-nm node fin and nanosheet FETs using novel process scheme

JS Yoon, S Lee, J Lee, J Jeong, H Yun… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
Process (systematic) variations of sub-5-nm node fin field-effect transistors (FinFETs) and
nanosheet field-effect transistors (NSFETs) were investigated thoroughly using fully …

Assessment of InAs/AlGaSb tunnel-FET virtual technology platform for low-power digital circuits

S Strangio, P Palestri, M Lanuzza… - … on Electron Devices, 2016 - ieeexplore.ieee.org
In this work, a complementary InAs/Al 0.05 Ga 0.95 Sb tunnel field-effect-transistor (TFET)
virtual technology platform is benchmarked against the projection to the CMOS FinFET 10 …

Digital/analog performance optimization of vertical nanowire FETs using machine learning

JS Yoon, S Lee, H Yun, RH Baek - IEEE Access, 2021 - ieeexplore.ieee.org
Vertical nanowire field-effect transistors (NWFETs) have been optimized to maximize digital
and analog performances using fully-calibrated TCAD and machine learning (ML) …

Electrostatic discharge protection: advances and applications

JJ Liou - 2017 - books.google.com
Electrostatic discharge (ESD) is one of the most prevalent threats to electronic components.
In an ESD event, a finite amount of charge is transferred from one object (ie, human body) to …